One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. The traditional development process might be insufficient to achieve the requirements of ultra-high-resolution features with low defect levels. The aim of this paper is to establish a process to achieve a good roughness, a low defectivity at a low EUV dose, and capability for extremely-high-resolution for high numerical aperture (NA) and hyper-NA EUV lithography. A new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR). ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient (higher exposure latitude (EL)) and reducing scums (fewer bridge defects). This new development method can also keep the resist profile vertical to mitigate the break defects. The performances of the conventional development and ESPERT™ were evaluated and compared using 0.33 NA EUV, 0.5 NA EUV, and electron beam (EB) exposures, for all line-space (LS), contact hole (CH), and pillar (PL) patterns. Using 0.33 NA EUV scanners on LS patterns, both bridge and break defects were confirmed to be reduced for all 32-nm-pitch, 28-nm-pitch, 26-nm-pitch LS patterns while reducing the EUV dose to size (DtS). In the electrical yield (1 meter length) test of breaks/bridges of 26-nm pitch structures, ESPERT™ reduced EUV dose while its combo yield was almost 100% over a wide dose range of 20mJ/cm². For CH patterns, in the case of 32-nm-pitch AEI (after etch inspection), EL was increased 7.5% up to 22.5%, while failure free latitude (FFL) was widened from 1-nm to 4-nm. A 16-nm-pitch LS pattern was successfully printed with 0.5 NA tool, while a 16-nm-pitch PL and an 18-nm-pitch CH patterns were also achieved with an EB lithography by ESPERT™. With ESPERT™, there was no pillar collapse observed for 12-nm half-pitch PL by 0.5 NA and 8-nm half-pitch PL by EB. With all the advantages of having a high exposure sensitivity, a low defectivity, and an extremely-high-resolution capability, this advanced development method is expected be a solution for high-NA EUV towards hyper-NA EUV lithography.
One of the key steps in the pattern formation chain of (extreme ultraviolet) EUV lithography is the development process to resolve the resist pattern after EUV exposure. A simple traditional development process might not be sufficient to achieve the requirements of an ultra-high-resolution feature with low defect levels in high numerical aperture (NA) EUV lithography. In our previous literature, a new development method named ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) has been introduced to improve the performance of metal oxide resists (MOR) for 0.33 NA EUV lithography by breaking the dose-roughness trade-off. In this work, this development technique was optimised for high-NA lithography to not only keep the advantages of previous ESPERTTM version, but also reduce the defect levels at a higher EUV sensitivity. This is made possible thanks to the capability of the new version of ESPERTTM that can easily remove the residue (undeveloped resist) at low exposure dose area to enhance the developing contrast. Using 0.33 NA EUV scanners at imec on 16-nm half-pitch (HP) line/space (L/S) patterns, with the new development method, EUV dose-to-size (DtS) was reduced roughly 16%, and total after-development-inspection (ADI) defects was reduced by a factor of approximately 7, simultaneously. In another condition, DtS was reduced from 44.2 to 28.4 mJ/cm² (an improvement of 36%), while the number of after-etch-inspection (AEI) single-bridge defects was reduced by half, simultaneously. Using the 0.5 NA exposure tool at Lawrence Berkeley National Laboratory with this new development method, the exposure sensitivity and line-width-roughness (LWR) were both improved by 30% and 21%, respectively. An 8-nm-HP L/S pattern was also successfully printed by this high NA tool. Using a 150 kV electron-beam (EB) lithography system, a 12-nm-HP of pillars was successfully printed on a 22-nm-thick MOR resist with ESPERTTM. With all the advantages of having a high exposure sensitivity, a low defectivity, and an ultra-high-resolution capability, this new development method is expected to be a solution for high-NA EUV lithography.
Bottom-up patterning approaches are gaining traction as the trade-offs between resolution, throughput, and cost continually run into limitations for advanced semiconductor manufacturing technologies. With these constraints in mind, we have previously explored spin-on selective deposition of polymers over microscale features for ultimate use in ALD technologies. Two methods have previously been explored. The first approach considered a spin-on self-assembled monolayer (SAM) protecting either a metal or dielectric pre-pattern followed by a selective spin-on polymer coating. The second approach customized a synthetic fluorinated polymer tailoring the surface energies to the structures and sizes of interest in order to achieve selective deposition. In this work, pre-patterned copper and dielectric patterns are explored for selective deposition using pitch ranges from 128nm – 1000nm. A combination of spin-on SAMs along with custom synthesized polymers are studied. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) are used to characterize final polymer coatings and the impact of polymer structure, solution concentration, and processing conditions will be discussed. Ultimately, it will be shown that the combination of both spin-on SAMs and custom synthesized polymers successfully results in selective deposition over nanometer scale patterns, increasing previous resolution by two orders of magnitude.
Resist Formulation Optimizer (RFO) is created to optimize resist formulation under EUV stochastic effects. Photosensitized Chemically Amplified ResistTM (PSCARTM) 2.0 reaction steps are included in the resist reaction model in RFO in addition to standard Chemically Amplified Resists (CAR) reaction steps. A simplified resist roughness calculation method is introduced in RFO. RFO uses “fast stochastic resist model” which uses continuous model information for stochastic calculation. “Resist component’s dissolution inhibition model” is also introduced for better prediction of different resist formulations in RFO. The resist component’s dissolution inhibition model is used for calculation of both Dissolution Inhibition Slope (DIS) and Dissolution Inhibition Deviation (DID). By dividing DID by DIS at a pattern edge, Line Edge Roughness (LER) can be predicted. The RFO performance is validated to give low residual errors after calibration even for different resist formulations. RFO is designed to optimize the resist formulation to minimize resist roughness as a cost function with keeping target CD. RFO suggests that PSCAR 2.0 with Polarity Switching photosensitizer precursor (POLAS) in combination with photosensitizer (PS) image enhancement may provide reduced resist roughness. Simulations using a calibrated rigorous stochastic resist model for S-Litho show a good prediction of PSCAR 2.0 process performance.
Photosensitized Chemically Amplified ResistTM (PSCARTM) has been demonstrated as a promising solution for a high sensitivity resist in EUV lithography mass production. This paper describes the successful calibration of a PSCAR resist model for deployment within rigorous lithography process simulation, capturing continuum as well as stochastic effects. Verification of the calibrated model parameters was performed with new patterns or with new resist formulations with good agreement. The reduction of required EUV dose of PSCAR resist while maintaining similar roughness levels have been achieved both from experimental result and from simulated result. The simulation of PSCAR continues to be a great tool for understanding, predicting, and optimizing the process of PSCAR.
Photosensitized Chemically Amplified ResistTM (PSCARTM) **2.0’s advantages and expectations are reviewed in this paper. Alpha PSCAR in-line UV exposure system (“Litho Enhancer”) was newly installed at imec in a Tokyo Electron Ltd. (TELTM)’s CLEAN TRACKTM LITHIUS ProTM Z connected to an ASML’s NXE:3300. Using the Litho Enhancer, PSCAR 2.0 sensitization preliminary results show that suppression of roughness enhancement may occur while sensitivity is increased. The calibrated PSCAR 2.0 simulator is used for prediction of resist formulation and process optimization. The simulation predicts that resist contrast enhancement could be realized by resist formulation and process optimization with UV flood exposure.
In order to lower the cost of ownership of EUV lithography, high sensitivity EUV resists , enabling higher throughput of EUV scanners are being explored. The concept that utilizes a Photosensitized Chemically Amplified ResistTM (PSCARTM) is a promising solution for achieving increased resist sensitivity, while maintaining other high performance characteristics of the material (i.e., resolution, line edge roughness (LER), exposure latitude). PSCAR uses a UV exposure after EUV exposure and selective absorption to meet these goals . Preliminary results have been discussed in previous papers 1-8.
PSCAR utilizes an area-selective photosensitization mechanism to generate more acid in the exposed areas during a UV exposure. PSCAR is an attempt to break the resolution, line-edge-roughness, and sensitivity trade-off (RLS trade-off) relationships that limit standard chemically amplified resists. The photosensitizer, which is generated in exposed area by a photoacid catalytic reaction, absorbs the UV exposure light selectively and generates additional acid in the exposed area only.
Material development and UV exposure uniformity are the key elements of PSCAR technology for semiconductor mass fabrication. This paper will review the approaches toward improvement of PSCAR resist process robustness. The chemistry’s EUV exposure cycle of learning results from experiments at imec will be discussed.
A new type of Photosensitized Chemically Amplified Resist (PSCAR) **: “PSCAR 2.0,” is introduced in this paper. PSCAR 2.0 is composed of a protected polymer, a “photo acid generator which can be photosensitized” (PS-PAG), a “photo decomposable base (quencher) which can be photosensitized” (PS-PDB) and a photosensitizer precursor (PP). With this PSCAR 2.0, a photosensitizer (PS) is generated by an extreme ultra-violet (EUV) pattern exposure. Then, during a subsequent flood exposure, PS selectively photosensitizes the EUV exposed areas by the decomposition of a PS-PDB in addition to the decomposition of PS-PAG. As these pattern-exposed areas have the additional acid and reduced quencher concentration, the initial quencher loading in PSCAR 2.0 can be increased in order to get the same target critical dimensions (CD). The quencher loading is to be optimized simultaneously with a UV flood exposure dose to achieve the best lithographic performance and resolution. In this work, the PSCAR performance when different quenchers are used is examined by simulation and exposure experiments with the 16 nm half-pitch (HP) line/space (L/S, 1:1) patterns. According to our simulation results among resists with the different quencher types, the best performance was achieved by PSCAR 2.0 using PS-PDB with the highest possible chemical gradient resulting in the lowest line width roughness (LWR). PSCAR 2.0 performance has furthermore been confirmed on ASML’s NXE:3300 with TEL’s standalone pre-alpha flood exposure tool at imec. The initial PSCAR 2.0 patterning results on NXE:3300 showed the accelerated photosensitization performance with PS-PDB. From these results, we concluded that the dual sensitization of PS-PAG and PS-PDB in PSCAR 2.0 have a potential to realize a significantly improved resist performance in EUV lithography.
Extreme ultraviolet lithography (EUVL, λ = 13.5 nm) continues to be one of the most important candidates for future technology nodes. For the insertion of EUV lithography into device mass production, higher sensitivity of EUV resists is helpful for better cost of ownership of the EUV tool and light source. However, obtaining low sensitivity (S), high resolution (R), and low line edge roughness (L) simultaneously is very difficult. Many previous experiments by lithographers proved the existence of this "RLS trade-off"1-2. This paper furthers the work related to Photosensitized Chemically Amplified ResistTM (PSCAR)TM**, a chemistry which is trying to break the "RLS tradeoff" relationship. This chemistry was introduced as a new chemically amplified lithographic concept and is accomplished in an in-line track tool with secondary exposure module connected to EUV exposure tool.
PSCAR is a modified CAR which contains a photosensitizer precursor (PP) in addition to other standard CAR components such as a protected polymer, a photo acid generator (PAG) and a quencher. In the PSCAR process, an improved chemical gradient can be realized by dual acid quenching steps with the help of increased quencher concentration. The addition of the PP, as well as other material optimization, offers more degrees of freedom for getting high sensitivity and low LER, but also makes the system more complicated. Thus coupling simulation and experimentation is the most rational approach to optimizing the overall process and for understanding complicated 2-D structures.
In this paper, we will provide additional background into the simulation of PSCAR chemistry, explore the effects of PSCAR chemistry on chemical contrast of complex structures (e.g. T structures, slot contacts, I/D bias for L/S), and explore the sensitivity enhancement levels capable while improving or maintaining lithographic performance. Finally, we will explore modifications of PSCAR chemistry on performance.
This paper proposes a promising approach to break the resolution (R), line-edge-roughness (LER), and sensitivity (S) trade-off (RLS trade-off) relationships that limit the ultimate lithographic performance of standard chemically amplified resists (CAR). This is accomplished in a process that uses a Photosensitized Chemically Amplified Resist (PSCAR) in combination with a flood-exposure in an in-line track connected to a pattern exposure tool. PSCAR is a modified CAR which contains a photosensitizer precursor (PP) in addition to other standard CAR components such as a protected polymer, a photo acid generator (PAG) and a quencher. In this paper, the PSCAR concept and the required conditions in resist formulation are carefully explained. In the PSCAR process, the sensitivity improvement is accomplished by PAG decomposition to selectively generate more acid at the pattern exposed areas during the flood exposure. The selective photosensitization happens through the excitation of the photosensitizer (PS) generated by the deprotection of the PP at the pattern exposed areas. A higher resist chemical gradient which leads to an improved resolution and lower LER values is also predicted using the PSCAR simulator. In the PSCAR process, the improved chemical gradient can be realized by dual acid quenching steps with the help of increased quencher concentration. Acid quenching first happens simultaneously with acid catalytic PP to PS reactions. As a result, a sharpened PS latent image is created in the PSCAR. This image is subsequently excited by the flood exposure creating additional acid products at the pattern exposed areas only. Much the same as in the standard CAR system, unnecessary acid present in the non-pattern exposed areas can be neutralized by the remaining quencher to therefore produce sharper acid latent images. EUV exposure results down to 15 nm half pitch (HP) line/space (L/S) patterns using a PSCAR resist indicate that the use of PSCAR has the potential to improve the sensitivity of the system while simultaneously improving the line-width-roughness (LWR) with added quencher and flood exposure doses. In addition, improved across-wafer critical dimension uniformity (CDU) is realized by the use of a PSCAR in combination with a flood exposure using pre α UV exposure module.
EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve
throughput has primarily been through a significant focus on source power which has been a continuing challenge
for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double
patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm
self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with
shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the
resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for
the patterned CD.
With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed
resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements
for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry
where the relaxation of both LER and CD together combined, give the resist formulation space a new target when
EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final
16nm half pitch target pattern to align with the industry needs.
If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow
proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed
process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added
costs associated with the double patterning process. This flow can then be shown to be an enabling approach for
many EUV applications.
KEYWORDS: Particles, Polymers, Line edge roughness, Monte Carlo methods, Diffusion, Photoresist developing, Photoresist materials, Lithography, 3D modeling, Molecules
A lattice-type Monte Carlo–based mesoscale model and simulation of the lithography process have been adapted to study the insoluble particle generation that arises from statistically improbable events. These events occur when there is a connected pathway of soluble material that envelops a volume of insoluble material due to fluctuations in the deprotection profile. The simulation shows that development erodes the insoluble material into the developer stream and produces a cavity on the line edge that can be far larger than a single polymer molecule. The insoluble particles can coalesce to form aggregates that deposit on the wafer surface. The effect of the resist formulation, exposure, postexposure bake, and development variables on particle generation was analyzed in both low- and high-frequency domains. It is suggested that different mechanisms are dominant for the formation of line-edge roughness (LER) at different frequencies. The simulations were used to assess the commonly proposed measures to reduce LER such as the use of low molecular weight polymers, addition of quenchers, varying acid diffusion length, etc. The simulation can be used to help set process variables to minimize the extent of particle generation and LER.
Line pattern collapse (LPC) becomes a critical concern as integrated circuit fabrication continues to advance towards
the 22 nm node and below. Tokyo Electron Limited (TEL) has been investigating LPC mitigation methods for many
years [1]. These mitigation methods include surfactant rinses to help reduce surface tension and Laplace pressures
forces that accompany traditional DIW rinses. However, the ability to explore LPC mitigation techniques at EUV
dimensions is experimentally limited by the cost and availability of EUV exposures. With this in mind, TEL has
adopted a combined experimental and simulation approach to further explore LPC mitigation methods.
Several analytical models have been proposed [2, 3, 4] for a LPC simulation approach. However, the analytical models
based on Euler beam theory are limited in the complexity of profile and material assumptions. Euler beam based
models are also now questionable because they are outside the beam theory's intended aspect ratio regime [5]. The
authors explore the use of finite element models in addition to Euler beam theory based models to understand resist
collapse under typical EUV patterning conditions. The versatility of current finite element techniques allows for
exploration of resist material property effects, profile and geometry effects, surface versus bulk modulus effects, and
rinse and surfactant rinse effects. This paper will discuss pattern-collapse trends and offers critical learning from this
simulation approach combined with experimental results from an EUV exposure system and TEL CLEAN TRACK
ACTTM 12 platform, utilizing state of the art collapse mitigation methods.
KEYWORDS: Systems modeling, Line edge roughness, Polymers, Diffusion, Calibration, Data modeling, Monte Carlo methods, Lithography, Molecular interactions, Stochastic processes
Current minimum feature sizes in the microelectronics industry dictate that molecular interactions affect process fidelity
and produce stochastic excursions like line edge roughness (LER). The composition of future resists is still unknown at
this point, and so simulation of various resist platforms should provide useful information about resist design that
minimizes LER. In the past, researchers developed a mesoscale model for exploring representative 248 nm resist
systems through dynamic Monte Carlo methods and adaptation of critical ionization theory. This molecular modeling
uses fundamental interaction energies combined with a Metropolis algorithm to model the full lithographic process (spin
coat, PAB, exposure, PEB, and development). Application of this model to 193 nm platforms allows for comparison
between 248 and 193 nm resist systems based on molecular interactions. This paper discusses the fundamental
modifications involved in adapting the mesoscale model to a 193 nm platform and investigates how this new model
predicts well-understood lithographic phenomena including the relationship between LER and aerial image, the
relationship between LER and resist components, and the impact of non-uniform PAG distribution in the resist film.
Limited comparisons between the 193 nm system and an analogous 248 nm platform will be discussed.
The development of double patterning processes/schemes are widely in progress for 2x nm node and beyond by using
193nm immersion lithography. It is realized that a resist shrink step is necessary in many double patterning process cases
due to the resolution limit of the 193nm immersion exposure tool.
As the development work progresses into the mass-product transition phase, the requirement for technical performances
has become more difficult to be achieved by existing resist shrink technologies.
In order to overcome these difficulties, we have developed "wet slimming" process based on our coater/developer
technologies including the platform. The process is optimized for CD uniformity and defectivity. The process also has
good robustness to the various possible resist materials and/or exposure conditions used by industry.
In this paper, we introduce the scheme of wet slimming process together with basic performance data such as CD
controllability, CD uniformity, defectivity and I-D bias. The evaluation data on actual double patterning processed
wafers is reported as well.
KEYWORDS: Particles, Polymers, Monte Carlo methods, Photoresist materials, Photoresist developing, Lithography, Molecules, Diffusion, 3D modeling, Line edge roughness
A lattice-type Monte Carlo based mesoscale model and simulation of the lithography process has been described
previously [1]. The model includes the spin coating, post apply bake, exposure, post exposure bake and development
steps. This simulation has been adapted to study the insoluble particle generation that arises from statistically
improbable events. These events occur when there is a connected pathway of soluble material that envelops a volume of
insoluble material due to fluctuations in the deprotection profile that occur during the post exposure bake [2].
Development erodes the insoluble material into the developer stream as an insoluble particle. This process may produce
a cavity on the line edge that can be far larger than a single polymer molecule. The insoluble particles generated may
coalesce in developer to form large aggregates of insoluble material that ultimately deposit on the wafer surface and the
tooling. The recent modifications made in mesoscale models for the PEB and dissolution steps, which have enabled this
study are briefly described. An algorithm that was used for particle detection in the current study is also discussed. The
effect of the resist formulation and the different lithographic steps, namely, exposure, post exposure bake and
development, on the extent of particle generation is analyzed. These simulations can be used to set process variables to
minimize the extent of particle generation.
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across
wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across
wafer systematic variations, compensation by exposure dose and/or post exposure bake (PEB) temperature have been
proposed. These compensation strategies often focus on a specific structure without evaluating how process
compensation impacts the CDU of all structures to be printed in a given design.
In one previous study limited to a single resist and minimal coater/developer and scanner variations, the authors
evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias
and CDU. For the process studied, it was found that using PEB temperature to control CD across wafer was preferable to
using dose compensation. In another previous study, the impact of resist design was explored to understand how resist
design, as well as coater/developer and scanner processing, impact process induced bias (PIB). The previous PIB studies
were limited to a single illumination case and explore the effect of PIB on only L/S structures.
It is the goal of this work to understand additionally how illumination design and mask design, as well as resist design
and coater/developer and scanner processing, impact process induced bias (PIB)/OPC integrity.
Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose and/or PEB temperature, have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation.
The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.
As semiconductor design rules continue to shrink, studies have begun on the 32nm-node and 22nm-node generations in semiconductor lithography technology in conjunction with the development of various fine-processing technologies. Research has been especially active in the development of high-NA193nm immersion lithography and EUV lithography for 32nm processes and beyond, but at the present stage of development, many technical issues have been reported. For example, in the contact-hole and via-hole pattern formation process in 193nm immersion lithography, it is difficult to maintain good resolution performance and process margins compared to line and space patterns. Poor resolution and other defects in the lithography process are major factors behind reduced yields in semiconductor production lines, and to prevent such defects, studies have begun on double patterning technology and shrink technology applied after resist-hole-pattern formation. Here, however, the need for reducing production processes and production costs have become major issues.
In response to these technical issues, we evaluated a variety of hole-shrink processes as candidates for a fine-hole-pattern formation technology, and as a result of this study, we succeeded in applying an original hole-shrink technology to the formation of 40nm hole patterns and beyond.
KEYWORDS: Critical dimension metrology, Monte Carlo methods, Semiconducting wafers, Photoresist processing, Lithography, Temperature metrology, Etching, Scanners, Process control, Reticles
As the industry transitions to the 45 nm node and beyond, requirements for critical dimension (CD) control
are getting extremely aggressive. Current 45 nm node specifications call for 2 nm or better CD uniformity
(CDU) on the gate level. For critical dimension control in this regime all measurable process effects must
be closely monitored and controlled. This includes such effects as etch uniformity, scanner dose and focus
consistency, post-exposure bake (PEB) plate uniformity, and incoming wafer variation such as wafer
warpage. The problem is that as the number of significant contributors to CDU continues to increase; the
number of parameters that can be used to control CDU has not.
To better understand how to achieve these increasingly stringent CDU targets, the authors have explored
how exposure and resist processing effects CD control. The goal of this work is to simulate how process
parameters such as dose and PEB temperature can be used to effectively control CD, while minimizing
unintended negative effects on thru pitch CD performance, MEEF, and other lithography process metrics.
In addition to traditional lithography metrics, the effect these process changes have on CDU is simulated
using a Monte Carlo technique.
KEYWORDS: Thin film coatings, Digital watermarking, Water, Semiconducting wafers, Lithography, Immersion lithography, Temperature metrology, Scanning electron microscopy, Diffusion, Bridges
The development of next-generation exposure equipment in the field of lithography is now underway as the demand
increases for faster and more highly integrated semiconductor devices. At the same time, proposals are being made for
lithography processes that can achieve finer pattern dimensions while using existing state-of-the-art ArF exposure
equipment.
Immersion exposure technology can use a high-refraction lens by filling the space between the exposed substrate and the
projection lens of the exposure equipment with a liquid having a high refractive index. At present, the development of
193-nm immersion exposure technology is proceeding at a rapid pace and approaching the realm of mass production.
However, the immersion of resist film in de-ionized water in 193-nm immersion exposure technology raises several
concerns, the most worrisome being the penetration of moisture into the resist film, the leaching of resist components
into the water, and the formation of residual moisture affecting post-processing. To mitigate the effects of directly
immersing resist in de-ionized water, the adoption of a top coat is considered to be beneficial, but the possibility is high
that the same concerns will rise even with a top coat.
It has been reported that immersion-specific defects in 193-nm immersion exposure lithography include "slimming,"
"large bridge," "swell," "micro-bridge," and "line pitch expansion," while defects generated by dry lithography can be
summarized as "residue," "substrate induced," "discoloration," and "pattern collapse." Nevertheless, there are still many
unexplained areas on the adverse effects of water seeping into a top coat or resist. It is vitally important that the
mechanisms behind this water penetration be understood to reduce the occurrence of these immersion-induced defects.
In this paper, we use top coats and resist materials used in immersion lithography to analyze the penetration and
diffusion of water. It is found that the water-blocking performance of protective-film materials used in immersion
lithography may not be sufficient at the molecular level. We discuss the diffusion of water in a top coat and its effects.
Topside anti-reflective coatings (TARC) are used in microelectronics fabrication to control standing wave formation during the patterning process. By changing the phase of the light that is reflected from the substrate, interference effects of thin photoresist films are minimized. Filtering and dispensing these fluids have proven to be difficult, as they are prone to micro-bubble formation due to surfactant additives. Surfactants will encapsulate micro-bubbles that form during filtration and dispense. The acidity of TARC is also of concern with regards to resist dark loss, especially at point of dispense. Minimization of TARC process defects is of paramount significance in a manufacturing environment. Reduced defect levels can increase overall yield and tool availability. In this study, we examined reducing the volume of trapped air and the resist dark loss associated with TARC acidity to prevent the formation of defects. Due to the inherent material properties of TARC, the handling, chemical priming, preventative maintenance, pump type, filter type and size, vent interval, filtration rate, idle/periodic dispense frequency methodology, and on-wafer dispense methodology must be considered to prevent in-film and surface defects associated with micro-bubbles and the TARC acidity. Defect reduction and increased tool availability was accomplished by examining and optimizing tool hardware and functionality, examining and optimizing filter media and size, examining and optimizing pump purge/vent sequences and frequency, improving overall pump knowledge, improving filter change procedure and maintenance, and understanding and reducing dark loss issues associated with acidity of TARC chemical.
As the integration of semiconductor devices continues, pattern sizes required in lithography get smaller and smaller. To achieve even more scaling down of these patterns without changing the basic infrastructure technology of current cutting-edge 193-nm lithography, 193-nm immersion lithography is being viewed as a powerful technique that can accommodate next-generation mass productions needs. Therefore this technology has been seriously considered and after proof of concept it is currently entering the stage of practical application. In the case of 193-nm immersion lithography, however, because liquid fills the area between the projection optics and the silicon wafer, several causes of concern have been raised - namely, diffusion of moisture into the resist film due to direct resist-water interaction during exposure, dissolution of internal components of the resist into the de-ionized water, and the influence of residual moisture generated during exposure on post-exposure processing. To prevent these unwanted effects, optimization of the three main components of the lithography system: materials, track and scanner, is required. For the materials, 193nm resist formulation improvements specifically for immersion processing have reduced the leaching and the sensitivity to water related defects, further benefits can be seen by the application of protective top coat materials. For the track component, optimization of the processing conditions and immersion specific modules are proven to advance the progress made by the material suppliers. Finally, by optimizing conditions on the 3rd generation immersion scanner with the latest hardware configuration, defectivity levels comparable to dry processing can be achieved. In this evaluation, we detail the improvements that can be realized with new immersion specific track rinse modules and formulate a hypothesis for the improvements seen with the rinsing process. Additionally, we show the current status of water induced immersion specific defect reduction using the latest advances in technology.
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