Lock-in amplifier (LIA) has been proposed as a detection technique for optical sensors because it can measure low signal in high noise level. LIA uses synchronous method, so the input signal frequency is locked to a reference frequency that is used to carry out the measurements. Generally, input signal frequency of LIA used in optical sensors is determined by modulation frequency of optical signal. It is important to understand the noise characteristics of the trans-impedance amplifier (TIA) to determine the modulation frequency. The TIA has a frequency range in which noise is minimized by the capacitance of photo diode (PD) and the passive component of TIA feedback network. When the modulation frequency is determined in this range, it is possible to design a robust system to noise. In this paper, we propose a method for the determination of optical signal modulation frequency selection by using the noise characteristics of TIA. Frequency response of noise in TIA is measured by spectrum analyzer and minimum noise region is confirmed. The LIA and TIA circuit have been designed as a hybrid circuit. The optical sensor is modeled by the laser diode (LD) and photo diode (PD) and the modulation frequency was used as the input to the signal generator. The experiments were performed to compare the signal to noise ratio (SNR) of the minimum noise region and the others. The results clearly show that the SNR is enhanced in the minimum noise region of TIA.
Surface plasmon resonance (SPR) sensor has been studied for high sensitivity optical biosensor as a single molecule
detection, virus detection, DNA sequencing etc. SPR sensor requires an ultra-small signal detection system that measures
very small intensity variation of reflected light along with the change of a refractive index near the sensor surface. In this
reason, lock-in detection method which is able to detect small signal buried in noise has been applied to SPR sensor. In
general lock-in detection method using multiplier and low pass filter measures DC value of output, and its sensitivity is
determined by 1/f noise at DC. Unlike the DC measurement we have proposed 2ω harmonic lock-in detection method
using multiplier and band pass filter. Sensitivity of the proposed lock-in detection method is much lower than 1/f noise at
DC. In this paper we will show that 2ω harmonic lock-in detection method for SPR sensor system providing the
sensitivity enhanced.
We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper
for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double
sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of
γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel
includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high
value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we
analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is
composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has
linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end
readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion.
Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS
detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.
KEYWORDS: Amplifiers, Signal detection, Sensors, Linear filtering, Optical amplifiers, Optoelectronics, Interference (communication), CMOS sensors, Signal to noise ratio, Phase shifts
We have designed dual lock-in amplifier (LIA) circuits in 0.18 μm CMOS technology for antibody-antigens
(IgG) detection using optoelectronics. The purpose of this work is to develop a lock-in amplifier integrated circuit (IC)
using the dual phase scheme that detect the phase difference between the input signal and the reference signal although a
phase shifter is absent. Our LIA consist of high gain amplifier, signal amplifier, and phase sensitive detection. Amplifier
structure is based on two-stage differential operational amplifier (op-amp) with RC Miller compensation technique. By
using the RC Miller compensation technique, we obtain 60° the phase margin of the op-amp. Here, the resistor works for
increasing the unit gain bandwidth and the capacitor works for increasing the phase margin. The lock-in amplifier
consume 8.6 mA from a 1.8 V supply.
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