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This paper contains simulation results with the Siemens EDA Calibre tool and demonstrates theoretical proof that alternative mask materials bring significant gain when compared to the tantalum-based mask absorber. Firstly, we optimized the source and aerial image intensity threshold on a set of predefined clips (with SMO techniques). Secondly, we applied ILT techniques to correct for the full chip mask based on a horizontal layout of a metal logic layer on imec’s roadmap. We then compare the tantalum-based mask with the alternative masks using imaging criteria, such as DoF (depth of focus), NILS (Normalized Image log slope), EPE (edge placement error), pattern shifts through focus, process variation band, source telecentricity errors, and MEEF (mask error enhancement factor) on a variety of features in the metal logic clip to maximize the overall process window.
Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing
The printability of the resulted OPC masks is checked through a model based manufacturing flow for the two pattering approaches. The final manufactured patterns are quantified by Edge Placement Error (EPE), Process Variation Band (PVBand), soft/hard bridging and pinching, Image Log Slope (ILS) and Common Depth of Focus (CDOF)
In this work we are comparing two potential pattering techniques for Back End Of Line (BEOL) metal layers in the 5nm technology node, the first technique is Single Exposure EUV (SE-EUV) with a Direct Patterning EUV lithography process, and the second one is Self-Aligned Quadruple Patterning (SAQP) with a hybrid lithography processes, where the drawn metal target layer is decomposed into a Mandrel mask and Blocks/Cut mask, Mandrel mask is printed using DUV 193i lithography process, while Block/Cut Mask is printed using SE-EUV lithography process. The pros and cons of each technique are quantified based on Edge-Placement-Error (EPE) and Process Variation Band (PVBand) measured at 1D and 2D edges. The layout used in this comparison is a candidate layout for Foundries 5nm process node.
To mitigate this risk, we propose an automated flow that is capable of producing large-scale realistic design content, and then optimizing the OPC recipe parameters to maximize the process window for this layout. The flow was tested with a triple-patterned 10nm node 1X metal level. First, design-rule clean layouts were produced with a tool called Layout Schema Generator (LSG). Next, the OPC recipe was optimized on these layouts, with a resulting reduction in the number of hotspots. For experimental validation, the layouts were placed on a test mask, and the predicted hotspots were compared with hardware data.
Study of air-bubble-induced light scattering effect on image quality in 193-nm immersion lithography
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