In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the
advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in
order to achieve the required precision and accuracy for wafer alignment performance.
ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the
computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di
platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity
matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment
marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of
alignment recipe settings.
Designing metrology targets that mimic process device cell behavior is becoming a common component in overlay process control. For an advanced DRAM process (sub 20 nm node), the extreme illumination methods needed to pattern the critical device features makes it harder to control the aberration induced overlay delta between metrology target and device patterns. To compensate for this delta, a Non-Zero-Offset is applied to the metrology measurement that is based on a manual calibration measurement using CD-SEM Overlay.
In this paper, we document how this mismatch can be minimized through the right choice of metrology targets and measurement recipe.
In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML’s Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.
Aberration sensitivity matching between overlay metrology targets and the device cell pattern has become a common requirement on the latest DRAM process nodes. While the extreme illumination modes used demand that the delta in aberration sensitivity must be optimized, it is effectively limited by the ability to print an optimum target that will meet detectability and accuracy requirements. Therefore, advanced OPC techniques are required to ensure printability and have optimal detectability performance while maintaining sufficient process window to avoid patterning or defectivity issues.
In this paper, we have compared various mark designs with real cell in terms of aberration sensitivity under the specific illumination condition. The specific illumination model was used for aberration sensitivity simulation while varying mask tones and target designs. Then, diffraction based simulation was conducted to analyze the effect of aberration sensitivity on the actual overlay values. The simulation results were confirmed by comparing the OL results obtained by diffraction based metrology with the cell level OL values obtained using Critical Dimension Scanning Electron Microscope.
In order to handle the upcoming 1x DRAM overlay and yield requirements, metrology needs to evolve to more accurately represent product device patterns while being robust to process effects. One way to address this is to optimize the metrology target design. A viable solution needs to address multiple challenges. The target needs to be resistant to process damage. A single target needs to measure overlay between two or more layers. Targets need to meet design rule and depth of focus requirements under extreme illumination conditions. These must be achieved while maintaining good precision and throughput with an ultra-small target. In this publication, a holistic approach is used to address these challenges, using computationally optimized metrology targets with an advanced overlay control loop.
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