Using electron beam direct write (EBDW) as a complementary approach together with standard optical lithography at
193nm or EUV wavelength has been proposed only lately and might be a reasonable solution for low volume CMOS
manufacturing and special applications as well as design rule restrictions. Here, the high throughput of the optical litho
can be combined with the high resolution and the high flexibility of the e-beam by using a mix & match approach (Litho-
Etch-Litho-Etch, LELE). Complementary Lithography is mainly driven by special design requirements for unidirectional
(1-D gridded) Manhattan type design layouts that enable scaling of advanced logic chips. This requires significant data
prep efforts such as layout splitting.
In this paper we will show recent results of Complementary Lithography using 193nm immersion generated 50nm
lines/space pattern addressing the 32nm logic technology node that were cut with electron beam direct write. Regular
lines and space arrays were patterned at GLOBALFOUNDRIES Dresden and have been cut in predefined areas using a
VISTEC SB3050DW e-beam direct writer (50KV Variable Shaped Beam) at Fraunhofer Center Nanoelectronic
Technologies (CNT), Dresden, as well as on the PML2 tool at IMS Nanofabrication, Vienna. Two types of e-beam
resists were used for the cut exposure. Integration issues as well as overlay requirements and performance improvements
necessary for this mix & match approach will be discussed.
KEYWORDS: Calibration, Monte Carlo methods, Photoresist processing, Electron beam lithography, Data modeling, Process modeling, Scanning electron microscopy, Computer simulations, Scattering, Chemically amplified resists
With the constantly improving maturity of e-beam direct write exposure tools and processes for applications in high volume
manufacturing, new challenges with regard to speed, throughput, correction and verification have to be faced. One objective
of the MAGIC high-throughput maskless lithography project [1] is the application of the physics-based simulation in a
virtual e-beam direct write environment to investigate proximity effects and develop comprehensive correction
methodologies [2]. To support this, a rigorous e-beam lithography simulator for the feature scale has been developed [3]. The
patterning behavior is determined by modeling electron scattering, exposure, and resist processing inside the film stack, in
analogy with corresponding simulation capabilities for the optical and EUV case. Some model parameters, in particular for
the resist modeling cannot be derived from first principles or direct measurements but need to be determined through a
calibration process.
To gain experience with the calibration of chemically amplified resists (CAR) for e-beam lithography, test pattern exposures
have been performed for a negative tone CAR using a variable-shaped beam writer operating at 50kV. A recently
implemented model calibration methodology has been applied to determine the optimum set of resist model parameters.
While the calibration is based on 1D (lines & spaces) patterns only, the model results are compared to 2D test structures for
verification.
KEYWORDS: Electron beam direct write lithography, Cadmium sulfide, Image processing, Printing, Line width roughness, Line edge roughness, Electron beams, Point spread functions, Photoresist processing, Metrology
For shortening the writing time, especially in shaped Electron Beam Direct Writing (EBDW), it is crucial to reduce
the number of shapes and the coverage of layout for exposure. The determination of conventional or reversed image
printing according to the process integration is one of the concerns for time and cost-effective process in the EBDW. We
have studied two different cases for the purpose above. First, the proximity effect correction (PEC) with dose
modification applied on each tone of resists, positive and negative, for the printing of conventional and reversed images.
The CDs that are obtained from the both printed images compared and are either with that from the simulations.
Secondly, the two different types of PEC, dose and shape modification, applied to a conventional image using an
identical point spread function (PSF). The line edge roughness (LER), line width roughness (LWR) and CDs in dose and
shape corrected conventional image pattern have been measured and compared. The MGS/PROXECCO was used for all
the preparation of exposure data mentioned above. In summary, we suggest the strategies of efficient PEC for the EBDW of contrasting images, propose the available method of PEC for the time-efficient EBDW, and for the further multiple EBDW developments.
Because of mask cost reduction, electron beam direct write (EBDW) is implemented for special applications such as rapid prototyping or small volume production in semiconductor industry. One of the most promising applications for EBDW is design verification by means of metal fix. Due to write time constrains, Mix & Match solutions have to be developed at smaller nodes. This study reports on several Mix and Match processes for the integration of E-Beam lithography into the optical litho process flow of Qimonda's 70 nm and 58 nm DRAM nodes. Different metal layers have been patterned in part with DUV litho followed by E-Beam litho using a 50 kV Vistec SB3050 shaped electron beam direct writer. All hardmask patterns were then simultaneously transferred into the DRAM stack. After full chip processing a yield study comprising electrical device characterization and defect investigation was performed. We show detailed results including CD and OVL as well as improvements of the alignment mark recognition. The yield of the E-Beam processed chips was found to be within the range of wafer-to-wafer fluctuation of the POR hardware. We also report on metal fix by electrical cutting of selected diodes in large chip scales which usually cannot be accessed with FIB methods. In summary, we show the capability of EBDW for quick and flexible design verification.
KEYWORDS: Semiconducting wafers, Lithography, Electron beams, Electrodes, Prototyping, Electron beam lithography, Electron beam direct write lithography, Silicon, Optical alignment, Photomasks
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam
solution for the 22 nm half-pitch node and beyond. PML2 is targeted on using hundreds of
thousands of individually addressable electron-beams working in parallel, thereby pushing
the potential throughput into the wafers per hour regime. With resolution potential of < 10
nm, PML2 is designed to meet the requirements of several upcoming tool generations.
KEYWORDS: Scatterometry, Metrology, Line edge roughness, Critical dimension metrology, Line width roughness, Semiconducting wafers, Electron beams, Electron beam direct write lithography, Lithography, Cadmium
Electron beam direct write (EBDW) can be utilized for developing metrology methods for future technology nodes. Due
to its advantage of high resolution and flexibility combined with suitable throughput capability, variable-shaped E-Beam lithography is the appropriate method to fabricate sub 40nm resist structures with accurately defined properties, such as critical dimension (CD), pitch, line edge roughness (LER) and line width roughness (LWR). In this study we present results of exposure experiments intended to serve as an important instrument for testing and fitting various metrology
and defect density measurement methods for future technology nodes. We successfully fabricated sub 40nm gratings with varying CD, pitch, programmed defects and LER/LWR. First metrology measurements by means of optical scatterometry on these dense structures show that variation of the signal response is sufficient to detect sub 10nm fluctuations with a satisfying repeatability.
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