Phase diversity (PD) is the special case of multiframe blind deconvolution algorithm, where an object is observed with a stack intentionally defocused image. The known defocused information between phases is used to estimate the object and aberration function. This paper presents a parallel three-dimensional (3-D) wavefront aberration estimation using blind deconvolution. We used multiplane PD for widefield fluorescence microscopy images of 3-D objects. Parallel multiplane PD yields a speedup factor of 4.33 with respect to the counterpart sequential algorithm for an image size of 256×256. We used the outcome of the PD algorithm to generate 3-D point cloud data from images from one view.
There has been many low-swing on-chip interconnect signaling techniques introduced to tackle the problem of inverse-scaling
effect of on-chip wires. This paper proposes a comparison framework using SPICE-based simulations on the
90nm technology node, which is needed to assess the effectiveness of a certain interconnect technique over the others
with a high degree of objectiveness and accuracy. Two low-swing techniques are included in the comparison, i.e.
conventional level converter (CLC) and current-mode signaling (CM). These techniques were chosen to represent
different driver and receiver topologies, where CLC uses lower driver supply voltage, while CM has a low impedance
termination at receiver end. In addition, an optimized full-swing repeater-based technique is included as a baseline for
comparison. The main contribution of this paper is the identification of circuit and wire design parameters that affects
performances the most, leading to a design guideline with reduced set of design variables for delay or energy
optimization of each technique. A simplified repeater performance estimation technique considering ramp input signals
is also proposed. Furthermore, trade-off between energy and delay using the optimization processes has been explored,
resulting in a more objective comparison of different interconnect techniques in the power-delay space. Results show
that optimized CLC (reduced voltage supply) repeaters can perform better in both terms of delay and power in its design
performance range.
KEYWORDS: Transceivers, Signal attenuation, Telecommunications, Endoscopes, Computer architecture, Amplifiers, Image resolution, Monte Carlo methods, Systems modeling, Pulse generators
This paper introduces an Ultra-Wideband (UWB) transceiver for in-vivo biotelemetry applications, especially for
wireless endoscope. A system modeling, simulation and design trade-off analysis for an UWB impulse radio transceiver
is presented that incorporates the human body attenuation effect, the IEEE 802.14a indoor channel model, and channel
noise to determine an optimum architecture for the given applications. Based on the system simulation using Matlab, the
severe effect from the human body attenuation has been identified and a non-coherent Transmit Reference (TR)
Transceiver architecture with differential Binary Phase Shift Keying (DBPSK) modulation was selected as the best
option for a communication link in biotelemetry applications. The transceiver consists of an all-digital transmitter with
H-bridge output stage type of Pulse Generator (PG), wideband inductorless resistive shunt feedback Low Noise
Amplifier (LNA) with thermal noise canceling, Gilbert mixer, Integrator, decision detector and Variable Delay
Controller (VDC). The performance characteristics of the PG, LNA and mixer are presented by the circuit simulation
results using 0.18μm digital CMOS technology.
In this paper we present the VLSI architecture for the buffer for tier-I of EBCOT encoder of JPEG2000. The buffer allows the integration of bit plane coder and arithmetic coder module employing concurrent symbol processing technique. The buffer architecture is optimized by exploiting the natural image statistics to optimally choose the buffer length parameter. The overall architecture is implemented using Altera FPGA and experimental results show a savings of 59% in the hardware cost with minimal reduction in the overall throughput.
In this paper, we propose a high performance direct bootstrapped CMOS latched driver circuit (J-driver). It is a 28% faster and occupies a 58% less active area as compared to a counterpart circuit (L-driver) using indirect bootstrap technique. In addition, our driver J-driver reduces the power consumption by a 2% in driving capacitive loads from 1pF to 6pF. The challenge in designing this latched driver is to appropriately trade-off performance against the active area.
Real time image processing is a key issue in nowadays multimedia applications. Image filtering and video coding are two basic applications in image processing. Their algorithms are computationally expensive due to both, the number of points of each frame to be processed, and the calculation complexity per point. The VLSI implementation of these algorithms leads to special architectures that are based on systolic arrays, and whose implementation is greedy in silicon area. In this paper, we propose a configurable and bidimensional pipelined VLSI architecture that supports mathematical morphology operations and the block matching algorithm. Remarkable advantages include low power consumption, and a regular and compact design (in terms of core active area) versus the traditional systolic architecture. The architecture is adequate for both morphological image filtering and video compression, depending on the hardware resources of the processing elements. The main advantage of this bidimensional pipeline architecture is the area saving compared with the systolic array implementation. Total area saving was presented in terms of the number of bits of the FIFO memories that can be eliminated. The proposed architecture was verified at high level in C++, at RTL level using Verilog and at C++/RTL level using DEMETER. Required cycle times was measured for a real time morphological filter per dilation/erosion operation, as a function of the incoming resolution. Physical layouts were obtained for the basic slice of the processing element and for the systolic array using the technology of 0,35 microns CMOS from AMS.
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