Dr. Serge Biesemans Profile

Dr. Serge Biesemans

at Tokyo Electron Europe Ltd

SPIE Involvement:

Author

Publications (16)

Proceedings Article | 25 May 2022 Presentation + Paper

Presentation + Paper

Buried power rail integration for CMOS scaling beyond the 3 nm node

A. Gupta, Z. Tao, D. Radisic, H. Mertens, O. Varela Pedreira, S. Demuynck, J. Bömmels, K. Devriendt, N. Heylen, S. Wang, K. Kenis, L. Teugels, F. Sebaai, C. Lorant, N. Jourdan, B. Chan, S. Subramanian, F. Schleicher, A. Peter, N. Rassoul, Y. Siew, B. Briggs, D. Zhou, E. Rosseel, E. Capogreco, G. Mannaert, A. Sepúlveda, E. Dupuy, K. Vandersmissen, B. Chehab, G. Murdoch, E. Altamirano Sanchez, S. Biesemans, Zs. Tőkei, E. Dentoni Litta, N. Horiguchi

Proceedings Volume 12056, 120560B (2022) https://doi.org/10.1117/12.2615641

KEYWORDS: Ruthenium, Metals, Molybdenum, Etching, Tungsten, Front end of line, Chemical mechanical planarization, Silicon

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Proceedings Article | 8 April 2019 Paper

Paper

PSCAR optimization to reduce EUV resist roughness with sensitization using Resist Formulation Optimizer (RFO)

Seiji Nagahara, Cong Que Dinh, Gosuke Shiraishi, Yuya Kamei, Kathleen Nafus, Yoshihiro Kondo, Michael Carcasi, Yukie Minekawa, Hiroyuki Ide, Yuichi Yoshida, Kosuke Yoshihara, Ryo Shimada, Masaru Tomono, Kazuhiro Takeshita, Serge Biesemans, Hideo Nakashima, Danilo De Simone, John Petersen, Philippe Foubert, Peter De Bisschop, Geert Vandenberghe, Hans-Jürgen Stock, Balint Meliorisz

Proceedings Volume 10960, 109600A (2019) https://doi.org/10.1117/12.2515187

KEYWORDS: Stochastic processes, Calibration, Extreme ultraviolet, Line edge roughness, 3D modeling, Extreme ultraviolet lithography, Switching

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Proceedings Article | 26 March 2019 Paper

Paper

Calibrated PSCAR stochastic simulation

Cong Que Dinh, Seiji Nagahara, Gousuke Shiraishi, Yukie Minekawa, Yuya Kamei, Michael Carcasi, Hiroyuki Ide, Yoshihiro Kondo, Yuichi Yoshida, Kosuke Yoshihara, Ryo Shimada, Masaru Tomono, Teruhiko Moriya, Kazuhiro Takeshita, Kathleen Nafus, Serge Biesemans, John Petersen, Danilo De Simone, Philippe Foubert, Peter De Bisschop, Geert Vandenberghe, Hans-Jürgen Stock, Balint Meliorisz

Proceedings Volume 10957, 109571O (2019) https://doi.org/10.1117/12.2515183

KEYWORDS: Modeling and simulation, Calibration, Ultraviolet radiation, Extreme ultraviolet lithography, Stochastic processes, Data modeling, Line width roughness, Extreme ultraviolet, Scanning electron microscopy

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Proceedings Article | 3 October 2018 Presentation + Paper

Presentation + Paper

EUV pupil optimization for 32nm pitch logic structures

D. Rio, V. Blanco, J.-H. Franke, W. Gillijns, M. Dusa, E. De Poortere, P. Van Adrichem, K. Lyakhova, C. Spence, E. Hendrickx, S. Biesemans, K. Nafus

Proceedings Volume 10809, 108090N (2018) https://doi.org/10.1117/12.2503321

KEYWORDS: Source mask optimization, Semiconducting wafers, Scanners, Logic, Extreme ultraviolet lithography, Reticles, Extreme ultraviolet

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Proceedings Article | 27 March 2018 Presentation + Paper

Presentation + Paper

EUV resist sensitization and roughness improvement by PSCAR with in-line UV flood exposure system

Seiji Nagahara, Michael Carcasi, Gosuke Shiraishi, Yuya Kamei, Kathleen Nafus, Yukie Minekawa, Hiroyuki Ide, Yoshihiro Kondo, Takahiro Shiozawa, Keisuke Yoshida, Masashi Enomoto, Kosuke Yoshihara, Hideo Nakashima, Serge Biesemans, Ryo Shimada, Masaru Tomono, Kazuhiro Takeshita, Teruhiko Moriya, Hayakawa Makoto, Ryo Aizawa, Yoshitaka Konishi, Masafumi Hori, Ken Maruyama, Hisashi Nakagawa, Masayuki Miyake, Tomoki Nagai, Satoshi Dei, Takehiko Naruoka, Motoyuki Shima, Toru Kimura, Geert Vandenberghe, John Petersen, Danilo De Simone, Foubert Philippe, Hans-Jürgen Stock, Balint Meliorisz, Akihiro Oshima, Seiichi Tagawa

Proceedings Volume 10586, 1058606 (2018) https://doi.org/10.1117/12.2297498

KEYWORDS: Ultraviolet radiation, Floods, Picosecond phenomena, Extreme ultraviolet lithography, Calibration, Extreme ultraviolet, Chemically amplified resists, Polymers, Image enhancement, Absorption

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Proceedings Article | 27 March 2018 Presentation + Paper

Presentation + Paper

Constructing a robust PSCAR process for EUV

Michael Carcasi, Seiji Nagahara, Gosuke Shiraishi, Yukie Minekawa, Hiroyuki Ide, Yoshihiro Kondo, Kosuke Yoshihara, Masaru Tomono, Ryo Shimada, Kazuhiro Takeshita, Teruhiko Moriya, Yuya Kamei, Kathleen Nafus, Serge Biesemans, Hideo Nakashima, Masafumi Hori, Ken Maruyama, Hisashi Nakagawa, Tomoki Nagai, Satoshi Dei, Masayuki Miyake, Takehiko Naruoka, Motoyuki Shima, Geert Vandenberghe, Danilo De Simone, Philippe Foubert, John Petersen, Akihiro Oshima, Seiichi Tagawa

Proceedings Volume 10583, 105831M (2018) https://doi.org/10.1117/12.2297370

KEYWORDS: Ultraviolet radiation, Extreme ultraviolet lithography, Extreme ultraviolet, Absorbance, Optical lithography, Absorption, Line edge roughness, Picosecond phenomena, Chemically amplified resists, Image processing

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Proceedings Article | 21 March 2018 Presentation + Paper

Presentation + Paper

Single exposure EUV of 32nm pitch logic structures: patterning performance on BF and DF masks

V. Blanco Carballo, J. Bekaert, J. H. Franke, R. H. Kim, E. Hendrickx, L. E. Tan, W. Gillijns, Y. Drissi, M. Mao, G. McIntyre, M. Dusa, M. Kupers, D. Rio, G. Schiffelers, E. De Poortere, J. Jia, S. Hsu, M. Demand, K. Nafus, S. Biesemans

Proceedings Volume 10583, 105830L (2018) https://doi.org/10.1117/12.2299639

KEYWORDS: Etching, Tin, SRAF, Optical lithography, Logic, Extreme ultraviolet, Photomasks, Stochastic processes, Scanning electron microscopy, Photoresist processing

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Proceedings Article | 20 March 2018 Presentation + Paper

Presentation + Paper

Tunable bandwidth for application-specific SAxP process enhancement

Paolo Alagna, Will Conley, Greg Rechtsteiner, Kathleen Nafus, Serge Biesemans, Gian Francesco Lorusso

Proceedings Volume 10587, 1058705 (2018) https://doi.org/10.1117/12.2300511

KEYWORDS: Light sources, Line width roughness, Semiconducting wafers, Optical lithography, Metrology, Line edge roughness, Etching, Lithography, Temporal coherence

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Proceedings Article | 30 March 2017 Presentation + Paper

Presentation + Paper

Image contrast enhancement of multiple patterning features through lower light source bandwidth

Paolo Alagna, Will Conley, Greg Rechtsteiner, Kathleen Nafus, Serge Biesemans

Proceedings Volume 10147, 101470N (2017) https://doi.org/10.1117/12.2263228

KEYWORDS: Optical lithography, Light sources, Lithography, Immersion lithography, Semiconductors, Image contrast enhancement, Deep ultraviolet, Semiconductor manufacturing, Manufacturing, Double patterning technology, Optical proximity correction, Semiconducting wafers, Photomasks, Metrology, Source mask optimization

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Proceedings Article | 27 March 2017 Presentation + Paper

Presentation + Paper

Photosensitized Chemically Amplified Resist (PSCAR) 2.0 for high-throughput and high-resolution EUV lithography: dual photosensitization of acid generation and quencher decomposition by flood exposure

Seiji Nagahara, Michael Carcasi, Gosuke Shiraishi, Hisashi Nakagawa, Satoshi Dei, Takahiro Shiozawa, Kathleen Nafus, Danilo De Simone, Geert Vandenberghe, Hans-Jürgen Stock, Bernd Küchler, Masafumi Hori, Takehiko Naruoka, Tomoki Nagai, Yukie Minekawa, Tomohiro Iseki, Yoshihiro Kondo, Kosuke Yoshihara, Yuya Kamei, Masaru Tomono, Ryo Shimada, Serge Biesemans, Hideo Nakashima, Philippe Foubert, Elizabeth Buitrago, Michaela Vockenhuber, Yasin Ekinci, Akihiro Oshima, Seiichi Tagawa

Proceedings Volume 10146, 101460G (2017) https://doi.org/10.1117/12.2258217

KEYWORDS: Extreme ultraviolet lithography, Chemically amplified resists, Floods, Lithography, Extreme ultraviolet, Line edge roughness, Image processing, Image enhancement, Ultraviolet radiation, Scanners, Picosecond phenomena, Polymers, Line width roughness, Stochastic processes

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Proceedings Article | 27 March 2017 Presentation + Paper

Presentation + Paper

Pattern uniformity control in integrated structures

Shinji Kobayashi, Soichiro Okada, Satoru Shimura, Kathleen Nafus, Carlos Fonseca, Serge Biesemans, Masashi Enomoto

Proceedings Volume 10146, 101461B (2017) https://doi.org/10.1117/12.2257868

KEYWORDS: Critical dimension metrology, Overlay metrology, Semiconductors, Error control coding, Optical lithography, Control systems, Manufacturing equipment, Lithography, Etching, Semiconducting wafers, Bridges, Line width roughness, Reticles, Statistical analysis, Stochastic processes, Data modeling, Digital electronics

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Proceedings Article | 21 March 2017 Presentation + Paper

Presentation + Paper

Co-optimization of lithographic and patterning processes for improved EPE performance

Mark Maslow, Vadim Timoshkov, Ton Kiers, Tae Kwon Jee, Peter de Loijer, Shinya Morikita, Marc Demand, Andrew Metz, Soichiro Okada, Kaushik Kumar, Serge Biesemans, Hidetami Yaegashi, Paolo Di Lorenzo, Joost Bekaert, Ming Mao, Christophe Beral, Stephane Larivière

Proceedings Volume 10149, 101490N (2017) https://doi.org/10.1117/12.2257979

KEYWORDS: Semiconducting wafers, Photoresist processing, Source mask optimization, Overlay metrology

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Complimentary lithography is already being used for advanced logic patterns. The tight pitches for 1D Metal layers are expected to be created using spacer based multiple patterning ArF-i exposures and the more complex cut/block patterns are made using EUV exposures. At the same time, control requirements of CDU, pattern shift and pitch-walk are approaching sub-nanometer levels to meet edge placement error (EPE) requirements. Local variability, such as Line Edge Roughness (LER), Local CDU, and Local Placement Error (LPE), are dominant factors in the total Edge Placement error budget. In the lithography process, improving the imaging contrast when printing the core pattern has been shown to improve the local variability. In the etch process, it has been shown that the fusion of atomic level etching and deposition can also improve these local variations. Co-optimization of lithography and etch processing is expected to further improve the performance over individual optimizations alone.

To meet the scaling requirements and keep process complexity to a minimum, EUV is increasingly seen as the platform for delivering the exposures for both the grating and the cut/block patterns beyond N7. In this work, we evaluated the overlay and pattern fidelity of an EUV block printed in a negative tone resist on an ArF-i SAQP grating. High-order Overlay modeling and corrections during the exposure can reduce overlay error after development, a significant component of the total EPE. During etch, additional degrees of freedom are available to improve the pattern placement error in single layer processes.

Process control of advanced pitch nanoscale-multi-patterning techniques as described above is exceedingly complicated in a high volume manufacturing environment. Incorporating potential patterning optimizations into both design and HVM controls for the lithography process is expected to bring a combined benefit over individual optimizations. In this work we will show the EPE performance improvement for a 32nm pitch SAQP + block patterned Metal 2 layer by cooptimizing the lithography and etch processes. Recommendations for further improvements and alternative processes will be given.

Proceedings Article | 21 March 2016 Paper

Paper

Analyzing block placement errors in SADP patterning

Shinji Kobayashi, Soichiro Okada, Satoru Shimura, Kathleen Nafus, Carlos Fonseca, Marc Demand, Serge Biesemans, Janko Versluijs, Monique Ercken, Philippe Foubert, Shinobu Miyazaki

Proceedings Volume 9779, 97791T (2016) https://doi.org/10.1117/12.2218597

KEYWORDS: Optical lithography, Overlay metrology, Process control, Error analysis, Semiconductors, Error control coding, Wafer inspection, Inspection, Manufacturing, Semiconducting wafers, System on a chip, Etching, Device simulation, Plasma etching, Scanning electron microscopy, Tin

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Proceedings Article | 17 April 2014 Paper

Paper

High speed EUV using post processing and self-aligned double patterning as a speed enhancement technique

Jerome Wandell, Anton deVilliers, Lior Huli, Serge Biesemans, Kathleen Nafus, Mike Carcasi, Jeff Smith, Dave Hetzer, Craig Higgins, Vinayak Rastogi, Erik Verduijn

Proceedings Volume 9048, 90483B (2014) https://doi.org/10.1117/12.2048862

KEYWORDS: Extreme ultraviolet, Etching, Double patterning technology, Extreme ultraviolet lithography, Atomic layer deposition, Line edge roughness, Line width roughness, Photoresist processing, Lithography, Resist chemistry

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Proceedings Article | 21 March 2007 Paper

Paper

Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node

Axel Nackaerts, Staf Verhaegen, Mircea Dusa, Hans Kattouw, Frank van Bilsen, Serge Biesemans, Geert Vandenberghe

Proceedings Volume 6521, 65210N (2007) https://doi.org/10.1117/12.713385

KEYWORDS: Transistors, Overlay metrology, Critical dimension metrology, Etching, Lithography, Semiconducting wafers, Statistical analysis, Instrument modeling, Logic

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Proceedings Article | 24 March 2006 Paper

Paper

Comprehensive approach to MuGFET metrology

G. Lorusso, P. Leray, T. Vandeweyer, M. Ercken, C. Delvaux, I. Pollentier, S. Cheng, N. Collaert, R. Rooyackers, B. Degroote, M. Jurczak, S. Biesemans, O. Richard, H. Bender, A. Azordegan, J. McCormack, S. Shirke, J. Prochazka, T. Long

Proceedings Volume 6152, 615219 (2006) https://doi.org/10.1117/12.656076

KEYWORDS: Metrology, Line width roughness, Scatterometry, Oxides, Semiconducting wafers, 3D metrology, Calibration, Transmission electron microscopy, Silicon, Optical proximity correction

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Showing 5 of 16 publications

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