High speed data links with low jitter and large bandwidth are essential for millimeter-wave (mmWave) communications. In this paper, an analog-domain 4-level pulse amplitude modulation (PAM4) baseband demodulation circuit with low data jitter and ultrahigh data rate was designed. In order to suppress the jitter caused by inter-symbol interference (ISI), a local feedback loop was introduced to extend the bandwidth of threshold slicer. A novel clock and data recovery (CDR) circuit architecture was proposed and optimized to extract the clock pulses with low jitter, thus improving the recovered data quality. A symmetric decoder performs an XOR logic operation to recover the least significant bit (LSB) of PAM4 signal, while the most significant bit (MSB) can be directly obtained from the middle-lane after retiming. The whole demodulation circuit was optimized based on IHP 130nm SiGe BiCMOS technology, and the simulation results indicate that our designed circuit can decode single-channel 50 Gbit/s PAM4 data streams into two 25 Gbit/s NRZ signals, and the peak-to-peak jitter is less than 0.1 UI.
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