The digital pattern generator (DPG) is a complex electron-optical MEMS that pixelates the electron beam in the reflective electron beam lithography (REBL) e-beam column. It potentially enables massively parallel printing, which could make REBL competitive with optical lithography. The development of the REBL DPG, from the CMOS architecture, through the lenslet modeling and design, to the fabrication of the MEMS device, is described in detail. The imaging and printing results are also shown, which validate the pentode lenslet concept and the fabrication process.
KEYWORDS: Electron beam lithography, Monte Carlo methods, Lithography, Line width roughness, Photomasks, Electron beams, Logic, Photoresist processing, Nanoimprint lithography, Semiconductor manufacturing
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm
logic (16 nm half pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam
Lithography (REBL) technology targeting high-volume 10 nm logic performance.
There are several potential applications for E-Beam Direct Write Lithography in high volume
manufacturing (HVM) Lithography. They range from writing full critical layers to the use as complementary
lithography in order to write cut masks for multiple patterning optical lithography. Two of the potential applications
for REBL with specific requirements on the writing strategy are contact layer and cut mask lithography. For these
two applications the number of electrons writing a single feature can be a concern if the resist sensitivity is high and
the process latitude is small. This paper will share calculations with respect to the needed and expected shot noise,
dose and focus latitude performance of a proposed REBL lithography system. The simulated results will be
compared to data taken on test structures. Predicted performance based on the simulations and test results of a
potential REBL system for contact layers and cut mask applications will be discussed.
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 10 nm logic (16 nm half
pitch) technology node and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL)
technology targeting high-volume 10 nm logic node performance. REBL uses a novel multi-column wafer writing
system combined with an advanced stage architecture to enable the throughput and resolution required for a NGL
system. Using a CMOS Digital Pattern Generator (DPG) chip with over one million microlenses, the system is capable
of maskless printing of arbitrary patterns with pixel redundancy and pixel-by-pixel grayscaling at the wafer. Electrons
are generated in a flood beam via a thermionic cathode at 50-100 keV and decelerated to illuminate the DPG chip. The
DPG-modulated electron beam is then reaccelerated and demagnified 80-100x onto the wafer to be printed.
Previously, KLA-Tencor reported on the development progress of the REBL tool for maskless lithography at and below
the 10 nm logic technology node. Since that time, the REBL team has made good progress towards developing the
REBL system and DPG for direct write lithography. REBL has been successful in manufacturing a CMOS controlled
DPG chip with a stable charge drain coating and with all segments functioning. This DPG chip consists of an array of
over one million electrostatic lenslets that can be switched on or off via CMOS voltages to pattern the flood electron
beam. Testing has proven the validity of the design with regards to lenslet performance, contrast, lifetime, and pattern
scrolling. This chip has been used in the REBL demonstration platform system for lithography on a moving stage in
both PMMA and chemically amplified resist. Direct imaging of the aerial image has also been performed by magnifying
the pattern at the wafer plane via a mag stack onto a YAG imaging screen. This paper will discuss the chip design
improvements and new charge drain coating that have resulted in a functional DPG chip and will evaluate the current
chip performance on the REBL system. Print results for line/space and device test patterns at the 100nm node will be
presented.
Maskless electron beam lithography has the potential to extend semiconductor manufacturing to the sub-10 nm technology node. KLA-Tencor is currently developing Reflective Electron Beam Lithography (REBL) for high-volume 10 nm logic (16 nm HP). This paper reviews progress in the development of the REBL system towards its goal of 100 wph throughput for High Volume Lithography (HVL) at the 2X and 1X nm nodes. In this paper we introduce the Digital Pattern Generator (DPG) with integrated CMOS and MEMs lenslets that was manufactured at TSMC and IMEC. For REBL, the DPG is integrated to KLA-Tencor pattern generating software that can be programmed to produce complex, gray-scaled lithography patterns. Additionally, we show printing results for a range of interesting lithography patterns using Time Domain Imaging (TDI).
Previously, KLA-Tencor reported on the development of a Reflective Electron Beam Lithography (REBL) tool for maskless lithography at and below the 22 nm technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam direct write lithography has been too slow for most lithography applications. Ebeam direct write lithography has been used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 22 nm technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVL.
KEYWORDS: Electron beam lithography, Semiconducting wafers, Electroluminescence, Lithography, Monte Carlo methods, Reflectivity, Electron beams, Direct write lithography, Silicon, Computer aided design
Maskless electron beam lithography can potentially extend semiconductor manufacturing to the 16 nm technology node
and beyond. KLA-Tencor is developing Reflective Electron Beam Lithography (REBL) targeting high-volume 16 nm
half pitch (HP) production. This paper reviews progress in the development of the REBL system towards its goal of 100
wph throughput for High Volume Manufacturing (HVM) at the 2X and 1X nm nodes. We will demonstrate the ability to
print TSMC test patterns with the integrated system in photoresist on silicon wafers at 45 nm resolution. Additionally,
we present simulation and experimental results that demonstrate that the system meets performance targets for a typical
foundry product mix.
Previously, KLA-Tencor reported on the development of a REBL tool for maskless lithography at and below the 16 nm
HP technology node1. Since that time, the REBL team and its partners (TSMC, IMEC) have made good progress towards
developing the REBL system and Digital Pattern Generator (DPG) for direct write lithography. Traditionally, e-beam
direct write lithography has been too slow for most lithography applications. E-beam direct write lithography has been
used for mask writing rather than wafer processing since the maximum blur requirements limit column beam current - which drives e-beam throughput. To print small features and a fine pitch with an e-beam tool requires a sacrifice in processing time unless one significantly increases the total number of beams on a single writing tool. Because of the continued uncertainty with regards to the optical lithography roadmap beyond the 16 nm HP technology node, the semiconductor equipment industry is in the process of designing and testing e-beam lithography tools with the potential for HVM.
In an effort to keep scaling at the speed of Moore's law, novel methods are being developed to facilitate advanced
semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches
beyond the current lithography resolution limit is spacer pitch splitting. This method typically involves patterning a
sacrificial gate pattern, then performing a standard spacer deposition and etch back process, after which the sacrificial gate
is removed and the remaining spacers themselves are used as the effective mask for the pattern transfer. Some of the key
advantages of this process are the ability to create sub-resolution lines and also the improvement in Line Edge Roughness
seen on the final pattern. However, there are certain limitations with this process, namely the ability to only pattern lines in
one dimension, and also the complexity of the metrology, where the final Critical Dimension result is a function of the
lithography condition from the sacrificial gate patterning, and also the various film layer depositions as well as the spacer
etch back process. Given this complexity, the accurate measurement of not only the spacer width but also the spacer shape
is important. In this work we investigate the use of scatterometry techniques to enable these measurements on leading edge
devices.
In an effort to keep scaling at the speed of Moores law, novel methods are being developed to facilitate advanced semiconductor manufacturing at the 32nm node and beyond. One such method for enabling the creation of dense pitches beyond the current lithography resolution limit is spacer pitch splitting. This method typically involves patterning a sacrificial gate pattern, then performing a standard spacer deposition and etch back process, after which the sacrificial gate is removed and the remaining spacers themselves are used as the effective mask for the pattern transfer. Some of the key advantages of this process are the ability to create sub-resolution lines and also the improvement in Line Edge Roughness seen on the final pattern. However, there are certain limitations with this process, namely the ability to only pattern lines in one dimension, and also the complexity of the metrology, where the final Critical Dimension result is a function of the litho condition from the sacrificial gate patterning, and also the various film layer depositions as well as the spacer etch back process. Given this complexity, the accurate measurement of not only the spacer width but also the spacer shape is important. In this work we investigate the use of scatterometry techniques to enable these measurements on leading edge devices.
Ion beam implantation of silicon with hydrogen is a method of producing thin silicon films for the manufacture of silicon on insulator (SOI) wafers. The implanted hydrogen depth profiles are traditionally measured using nuclear reaction analysis (NRA) or secondary ion mass spectrometry (SIMS) which have the disadvantages of requiring specialized equipment and, in the case of SIMS, being a destructive measurement. In the current work, a simplified method of measuring the depth profile of implanted hydrogen ions in silicon has been developed. Using a spectroscopic ellipsometer, optical data are collected from hydrogen implanted silicon wafers in a non-contact and non-destructive manner. The ellipsometric data from 600-980 nm wavelength are then analyzed by modeling the damage as a graded sub-surface layer in the silicon. By fitting this model to the experimental data, values for the depth of the implantation and the width of the implantation distribution can be extracted. This method offers the advantages of being repeatable, fast, and non-destructive, as well as using a piece of metrology equipment readily available in most semiconductor fabs. The method has been tested over a range of implant energies (24-92 keV) and hydrogen doses and shows excellent correlation to traditional NRA measurements for implant depth profile.
We report here on initial results for the characterization and modeling of 100 nm lithography features based on normal incidence spectroscopic ellipsometry and polarized reflectometry. In this work, a set of wafers was exposed as focus-exposure and separate focus or exposure matrices to create resists patterns with extremely small variations in CD and pattern shape. These variations were generated along scan, within slit and across full wafer. Optical CD scatterometry was used to extract critical feature parameters such as complete shape and associated linear dimensions. Extracted pattern parameters were compared to FIB sections and used to predict lithography process latitudes. We explore effects of using multi normal incidence ellipsometric signals with various profile models to increase accuracy of extracted lithography parameters. We propose a metric for identifying effects of scan-dynamic does and focus variations upon slit-intrafield and scan- intrafield CD errors. This has been tested over ranges of defocus and exposure that are larger than typical FE latitudes of 100 nm features. As a result of spectroscopic scatterometry calculations of pattern shape, we identified pattern shape variations caused by dose and defocus that are clearly coupled to changes in feature size. These could be used for unique determination of dose-focus deviations using scatterometry-extracted information from measurements of a grating structure.
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