Low dose X-ray image sequences, as obtained in fluoroscopy, exhibit high levels of noise that must be
suppressed in real-time, while preserving diagnostic structures. Multi-step adaptive filtering approaches, often
involving spatio-temporal filters, are typically used to achieve this goal. In this work typical fluoroscopic image
sequences, corrupted with Poisson noise, were processed using various filtering schemes. The noise
suppression of the schemes was evaluated using objective image quality measures. Two adaptive spatio-temporal
schemes, the first one using object detection and the second one using unsharp masking, were
chosen as representative approaches for different fluoroscopy procedures and mapped on to Texas
Instrument's (TI) high performance digital signal processors (DSP). The paper explains the fixed point design
of these algorithms and evaluates its impact on overall system performance. The fixed point versions of these
algorithms are mapped onto the C64x+TM core using instruction-level parallelism to effectively use its VLIW
architecture. The overall data flow was carefully planned to reduce cache and data movement overhead,
while working with large medical data sets. Apart from mapping these algorithms on to TI's single core DSP
architecture, this work also distributes the operations to leverage multi-core DSP architectures. The data
arrangement and flow were optimized to minimize inter-processor messaging and data movement overhead.
DSP chips are gaining importance in ultrasound applications as the need for portability and low power grows. One of the
more computationally demanding applications for ultrasound involves estimating blood flow characteristics using
Doppler techniques. This ultrasound mode, called color Doppler ultrasound, is used to diagnose many conditions like
blood clots, valve defects and blocked arteries. This work looks at mapping some typical color Doppler algorithms onto
Texas Instruments' (TI's) high performance C64x+(TM) core. The algorithms include RF demodulation, wall filtering and
flow power, velocity and turbulence estimation. This paper starts with a general technique for analyzing algorithm
complexity in terms of CPU instruction cycles on VLIW architectures like the C64x+(TM). It then applies this technique to
Doppler processing algorithms, explains their mapping to the C64x+(TM) architecture and derives lower bounds for the
computational complexity for these algorithm kernels. For each of these algorithms, these estimates are finally compared
to actual implementations, and various implementation tradeoffs will be illustrated. Based on these implementations, it
will be shown that these algorithms can run on TI's C64x+(TM) based DSPs using a fraction of the available processing
power.
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