KEYWORDS: Photoresist materials, Line edge roughness, Critical dimension metrology, Metals, Optical lithography, Double patterning technology, Capacitance, Photoresist processing, Front end of line, Back end of line, Etching, Transistors
The effects of photoresist sidewall profile and LER on two representative integration schemes were studied through 3D
virtual fabrication: Front-End of Line (FEOL) Fin formation and Back-End of Line (BEOL) Metal line definition. Both
of these processes use self-aligned double patterning (SADP) in pattern definition, and affect the circuit performance
through MOSFET channel shape and parasitic capacitance respectively. In both cases we imposed LER and sidewall
roughness on the photoresist that defines the mandrel at the initial step of the SADP flow using SEMulator3D. The LER
followed a Gaussian correlation function for a number of amplitude and correlation length values. The sidewall profile
emulated the bulb-shaped pattern that is reported in experimental works. The taper angle and roughness amplitude of this
shape were varied to isolate its components. In each of these cases, we have found direct evidence of resist sidewall
profile impact on variability degradation in CD and electrical performance. Special care should be placed on controlling
resist profile through optimization of exposure and development schemes.
For directed self-assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of self-aligned quadruple patterning with Liu–Nealey chemoepitaxy on a 14-nm dynamic random access memory (DRAM) process. To quantify the impact of this module replacement, we investigated a key process yield metric for DRAM, interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally packed capacitors patterned with an array of diblock copolymer cylinders in place of fourfold litho-etch (LE4) patterning.
KEYWORDS: Line edge roughness, Line width roughness, Etching, Lithography, Process modeling, Optical lithography, Back end of line, Deposition processes, Spatial frequencies
For the first time, process impact on line-edge roughness (LER) and line-width roughness (LWR) in a back-end-of-line (BEOL) self-aligned quadruple patterning (SAQP) flow has been systematically investigated through predictive 3D virtual fabrication. This frequency dependent LER study shows that both deposition and etching effectively reduce high frequency LER, while deposition is much more effective in reducing low frequency LER. Spacer-assisted patterning technology reduces LWR significantly by creating correlated edges, and further LWR improvement can be achieved by optimizing individual process effects on LER. Our study provides a guideline for the understanding and optimization of LER and LWR in advanced technology nodes.
For Directed Self-Assembly (DSA) to be deployed in advanced semiconductor technologies, it must reliably integrate into a full process flow. We present a methodology for using virtual fabrication software, including predictive DSA process models, to develop and analyze the replacement of SAQP patterning with LiNe chemoepitaxy on a 14nm DRAM process. To quantify the impact of this module replacement, we investigate a key process yield metric for DRAM: interface area between the capacitor contacts and transistor source/drain. Additionally, we demonstrate virtual fabrication of the DRAM cell’s hexagonally-packed capacitors patterned with an array of diblock copolymer cylinders in place of LE4 patterning.
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