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In this work we explore the different multipatterning options for lines and blocks at pitches below 20 nm. As such, we will demonstrate and compare three different patterning options to enable 16 nm pitch gratings: 193i-based SAOP, EUV-based SADP and EUV-based SAQP. Finally, we will also elaborate on a self-aligned patterning scheme which does not define lines and blocks sequentially anymore but integrates them in a mixed mode. This patterning approach (SALELE) makes use of two LE masks and two self-aligned block masks. We will present its development status at relaxed pitch (28 nm) and discuss its advantages for future technology nodes.
Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers.
In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.
To be effective during the lithographic EUV material screening phase for such tight pitches, it is necessary to implement complementary metrology analyses that can provide precise information on the resist roughness and a quick feedback on the quantification of nano-failures (nano-bridges, broken lines, merging or missing contacts) induced by a stochastic EUV patterning regime, the random nature of the light-matter interaction and consequent chemical reactions. Beside the traditional approach to characterize a resist with metrics as exposure latitude (EL%), depth of focus (DoF) and line-edge-roughness (LER) based on CDSEM measurements, we have used the power spectra density (PSD) [4] to get an unbiased value of the resist line roughness (LWR and LER) by using Fractilia metroLERTM commercial software. Further, we have used Stochalis imec software [5] to quantify patterning nano failures providing an early stage assessment on the patterning fidelity of the examined resists.
We present the resist characterization results for 32nm dense line-space pattern on different substrates and for 36nm dense and orthogonal contact hole pitch pattern for different photoresists. Two positive tone chemically amplified (CA) resists have been identified at the exposure dose of 45mJ/cm2 and 33mJ/cm2 for logic (pitch 32nm dense line/space) and memory (pitch 36nm dense contact holes) use cases, respectively.
Even in a 1D design style, single exposure of the 16 nm half-pitch M2 layer is very challenging for EUV lithography, because of its tight tip-to-tip configurations. Therefore, the industry is considering the hybrid use of ArFi-based SAQP combined with EUV Block as an alternative to EUV single exposure. As a consequence, the EUV Block layer may be one of the first layers to adopt EUV lithography in HVM.
In this paper, we report on the imec iN7 SAQP + Block litho performance and process integration, targeting the M2 patterning for a 7.5 track logic design. The Block layer is exposed on an ASML NXE:3300 EUV-scanner at imec, using optimized illumination conditions and state-of-the-art metal-containing negative tone resist (Inpria). Subsequently, the SAQP and block structures are characterized in a morphological study, assessing pattern fidelity and CD/EPE variability. The work is an experimental feasibility study of EUV insertion, for SAQP + Block M2 patterning on an industry-relevant N5 use-case.
Regarding the metal 2 layer, imec is evaluating two integration approaches: EUV single print and SAQP+EUV Block. Extensive work is reported on both approaches2,3. The work detailed in this paper will deal about the computational work done prior to tape-out for the EUV direct print option.
We will discuss the EUV source mask optimization for an ASML NXE:3300 EUV scanner. Afterwards we will shortly touch upon OPC compact modeling and more extensively on OPC itself. Based on the current design rules and MRC, printability checks indicate that only limited process windows are obtained. We propose ways to improve the printability through MRC and design. Applying those changes can potentially lead to a sufficient process window.
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