The reliability of semiconductor devices is a key indicator to measure the reliability of electronic devices. In view of the difficulties in modeling, low prediction accuracy and long prediction period faced by traditional reliability prediction methods of semiconductor devices, a deep learning based reliability prediction method of semiconductor devices is proposed in this paper. Besides, the accelerated degradation test data set of bipolar transistors under constant stress of temperature and humidity is analyzed, and the failure sensitive parameter Icbo of transistors is determined. The Data Fitting, LSTM, GRU and GRU-LSTM models are used to predict the trend of Icbo degradation of three transistors which are randomly selected from data set. The prediction results of device storage life using data fitting method and GRU-LSTM model are compared, and it is found that the overall distribution of device storage life predicted by the two methods is similar, but the prediction accuracy of GRU-LSTM model is higher and more suitable to the actual situation. This paper can provide some reference for predicting the reliability of domestic semiconductor devices.
Quickly predicting the remaining useful life of bipolar transistors is an effective means of assessing their health and reliability. Aiming at the problems of high modeling difficulty and poor fitting accuracy in the traditional physical model method and data fitting method, this paper proposes a reliability life prediction method for bipolar transistors based on deep learning. Firstly, the experiment is carried out with the accelerated storage experimental data of transistors in the Microelectronics Reliability Laboratory of Beijing University of Technology, and the reverse leakage current ICBO is selected as the failure sensitive parameter, and a reasonable failure judgment is set. The lifetime of the sample is calculated; Secondly, the average lifetime under three common distributions is given, and combined with the Peak temperature and humidity model, the storage lifetime of the transistor under natural storage conditions is extrapolated; finally, the mean absolute error (MAE) and mean square error (MSE) are selected as evaluation functions, and the life prediction results of the deep learning model and the data fitting method are compared. The results show that compared with the data fitting method, the MAE of the life prediction results of the deep learning model decreases by 82.00%, and the MSE decreases by 98.16%, which verifies the effectiveness of the method.
KEYWORDS: Convolution, Field programmable gate arrays, Detection and tracking algorithms, Data modeling, Digital signal processing, Data storage, Algorithm development, Energy efficiency, Target detection, Thulium
YOLO (You Only Look Once) of target detection algorithms have complex model structure and large computation. However, in practical application scenarios, they not only need to meet the task requirements of low latency and low power consumption, but also face problems such as difficult deployment and long development cycle of YOLO algorithms. Based on the flexibility of embedded CPU software design and the advantages of Field Programmable Gate Array (FPGA) parallel computing, combined with the structural characteristics of YOLO algorithm, a universal hardware accelerator software/hardware co-design method for rapid deployment of YOLO algorithm is proposed to solve the above problems. In the hardware acceleration design, multi-channel parallel internal and external storage interaction, model parameter reordering, fixed-point, multi-dimensional parallelism tiling and other acceleration optimization techniques are adopted. In the software driver design, multiple versions of YOLO algorithm are compatible to achieve rapid deployment. Zynq7000 is used as the hardware platform to implement a YOLO algorithm universal hardware accelerator system with low delay and low power consumption. The results show that the energy efficiency ratio of this system can be improved by 132x compared with PC CPU and 120x compared with embedded CPU while implementing YOLOv4-tiny algorithm.
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