This paper demonstrates a full-chip OPC correction flow based on deep-learning etch model in a DUV litho-etch case. The flow leverages SEM metrology (eP5 fast E-beam tool, ASML-HMI) to collect massive data, automated metrology software (MXP, ASML-Brion) to extract high quality gauges, and deep-learning etch modeling (Newron etch, ASML-Brion) to capture complicated etch behaviors. The model calibration and verification are performed using a combined data from a test and real chip wafer to ensure sufficient pattern coverage. The model performance of Newron etch is benchmarked against a term-based etch model, wherein Newron etch model shows significant accuracy improvement in the model calibration (<50% for test patterns and <35% for real chip pattern). The Newron etch model is proven stable with a comparable performance in the model verification. Particularly, strong loading effects from underlying sublayer are observed in the full chip wafer, and effectively captured by the Newron etch with a sublayer-aware model form. The calibrated Newron etch model is successfully applied in a model-based etch OPC tape-out with new mask design rules but the same litho-etch process conditions. Compared to the term-based model, Newron etch also shows significant accuracy improvement.
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