This papers presents a high-speed, latched comparator implemented in industrial 28 nm FD-SOI technology. A novel approach to counter the mismatch is proposed. The solution employs trimming the threshold voltage by means of modulating of back-gate polarization of FD-SOI transistors. The comparator is a first step towards the design of a complete 4-bit FLASH analog-to-digital converter, with a sampling frequency of 10 GHz.
This papers presents a classic fully differential operational transconductance amplifier (FDOTA) implemented in industrial 28 nm FD-SOI (Fully-Depleted SOI) technology. A novel approach to minimized the FDOTA offset voltage is proposed. The solution employs the unique feature of FD-SOI technology - back-gate biasing - combined with modern compensation methodology. The proposed method results in considerable design overhead. However, this offset cancellation approach is very effective and allows to improve FDOTA performance when classic techniques reach their limits.
In this papers, a fully differential operational transconductance amplifier (OTA) implemented in 65 nm CMOS
technology is analyzed to determine which component of the calibration circuitry is most susceptible to manufacturing process disturbances and thus impairs robustness of the calibration methodology. The average offset
voltage of the OTA can be significantly reduced. It has been shown that effectiveness of the calibration methodology is limited by the offset voltage of the comparator that calculates sign of the OTA offset voltage.
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