Pushing optical microlithography towards the 32nm node requires hyper-NA immersion optics in combination with advanced illumination, polarization, and mask technologies. Novel approaches in model-based optical proximity correction (OPC) and sub-resolution assist feature (SRAF) optimization are required to not only produce correct feature shapes at the nominal process condition but also to maintain edge placement tolerances within spec limits under process variations in order to ensure a finite process window. In addition, it is becoming increasingly important to consider interactions between multiple layers when performing correction in order to ensure electrical viability. In this paper we discuss the application of a model based process-window-aware and interlayer-aware integrated OPC system on 32nm node patterns. Process window awareness will be demonstrated for main feature correction by taking into account image-based modeling at multiple defocus and dose conditions. In addition, interlayer-awareness will be demonstrated by correction that takes into account the effects of active width on gate CD and of contact overlap with metal, gate, and active. The results show an improvement over "non-aware" OPC in gate CD control, in contact overlap, and in overall process margin. In addition, PW aware correction is demonstrated to prevent potential catastrophic failures at extreme PW conditions.
Due to complex interconnect wiring scheme and constraints from process rules, systematic defects such as pattern necking and bridging are a major concern for metal layers. These systematic defects or "weak spots" can be major yield detractors in IC manufacturing if not properly addressed. These defects can occur even in cases where model-based OPC has been implemented, as well as a variety of process rules for margin insurance. Determining how to improve the marginalities or "weak spots" becomes a key factor for enhancing product yields. This paper will address several root causes for pattern induced defects and present solutions to a variety of weak spots including "T-shape," "H-shape," "Thin-Line," and "Bowling Pin" defects during 65nm product development at TI. Through case studies, we demonstrate how to successfully provide DFM (Design for Manufacturing) by using Resolution Enhancement Techniques (RET) tools to avoid and minimize the weak spots. Furthermore, process techniques to improve printability for some of the weak spots as applied to 65nm reticle sets will be discussed. An integrated scheme aiming at optimization of design rules and process rules is proposed.
Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 nm dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.
The continued downscaling of semiconductor fabrication ground rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment. Past experiences indicate that good alignment depends largely on alignment signal quality, which, however, can be strongly affected by chip design and various fabrication processes. Under some extreme circumstances, they can even be reduced to the non- usable limit. Therefore, a systematic understanding of alignment marks and a method to predict alignment performance based on mark design are necessary. Motivated by this, we have performed a detailed study of bright field segmented alignment marks that are used in current state-of- the-art fabrication processes. We find that alignment marks at different lithographic levels can be organized into four basic categories: trench mark, metal mark, damascene mark, and combo mark. The basic principles of these four types of marks turn out to be so similar that they can be characterized within the theoretical framework of a simple model based on optical gratings. An analytic expression has been developed for such model and it has been tested using computer simulation with the rigorous time-domain finite- difference (TD-FD) algorithm TEMPEST. Consistent results have been obtained; indicating that mark signal can be significantly improved through the optimization of mark lateral dimensions, such as segment pitch and segment width. We have also compared simulation studies against experimental data for alignment marks at one typical lithographic level and a good agreement is found.
State of the art exposure tools today are expected to operate at very small k1 factors for semiconductor manufacturing, imposing very tight requirements on lens performance. To evaluate the lens quality with respect to coma and other asymmetric aberrations, two types of monitors, 5-line monitor structure and box in box structure, are used. For a 5-line monitor structure lens coma assessment is achieved by measuring the difference of printed CD between the left most outer and the right most outer line. The principle for box in box structure is to utilize the effect of feature size-dependent image placement. Coma assessment can be achieved by measuring overlay shift between a frame of target line width and a square of larger dimension.
A double exposure technique, so called nano-stepping, was investigated to evaluate its benefit for very dense features to reduce line shortening, improve pattern fidelity and resolution capability. The technique involves relaxing the pitch of dense patterns in one dimension and filling in the missing patterns by exposing the same reticle again, offset by an appropriate amount. This method suffers only small throughput loss compared to conventional dual reticle exposure techniques. For 1D patterns, 100 nm lines and spaces can be printed with a 248 nm exposure tool and a half tone mask. Dense 2D contacts with various length to width ratios can be achieved with minimum distance to adjacent neighbors.
A special class of post-development defects, referred as Circular Surface Defects (CSDs), has been reported. Up to now, no resist is immune to CSD printing, including eight commercial KrF resists (from two vendors) and six early samples of ArF resists (from five vendors). An extensive study on the CSDs was conducted on a KrF Resist A, in term of its origin, formation and removal mechanism. Photoacid generators (PAGs) are proved to be a primary contributor to the CSDs. The origin of CSDs is believed to be PAG aggregation along with other hydrophobic components, resulting in formation of microemulsions in the developer. The aggregates have limited solubility in aqueous base developer, and could redeposit on the wafer surface during development. We propose one major defect removal mechanism, or 'Stripping' mechanism. This mechanism is related to resist film thickness loss, which aids in stripping potential defects from the resist surface, or reducing the probability of defect deposition.
Xiaoming Yin, Alfred Wong, Donald Wheeler, Gary Williams, Eric Lehner, Franz Zach, Byeong Kim, Yuzo Fukuzaki, Zhijian Lu, Santo Credendino, Timothy Wiltshire
The impact of alignment mark structure, mark geometry, and stepper alignment optical system on mark signal contrast was investigated using computer simulation. Several sub-wavelength poly silicon recessed film stack alignment targets of advanced memory products were studied. Stimulated alignment mark signals for both dark-field and bright-field systems using the rigorous electromagnetic simulation program TEMPEST showed excellent agreement with experimental data. For a dark-field alignment system, the critical parameters affecting signal contrast were found to be mark size and mark recess depth below silicon surface. On the other hand, film stack thickness and mark recess depth below/above silicon surface are the important parameters for a bright-field alignment system. From observed simulation results optimal process parameters are determined. Based on the simulation results some signal enhancement techniques will be discussed.
Multiple contact hole resist samples from a variety of DUV resist suppliers, including both acetal and ESCAP chemistries are evaluated on an organic anti-reflective under layer (ARC) using an attenuated phase shift mask (APSM). One sample exhibited excellent surface inhibition and superior lithographic performance for patterning contact holes of 0.2 micrometers imaging size. For most of resists, the process windows are limited by unwanted sidelobe printing through focus. The sensitivity of sidelobe printing to focus can be attributed to lens aberrations. For the first time, we prose to use Depth-of-focus (DOF) loss PWLdof and Exposure latitude (EL) loss PWLel to characterize resists surface inhibition, as well discovered that DOF loss is a sensitive measure of surface inhibition. Similar lithographic performance is obtained from acetal and ESCAP based materials. The two ESCAP resists EB3 and EA2 have better oxide etch resistance than the acetal resist AC1. The top surface reticulation is observed on ESCAP resist EB3 and EA2 during the oxide etch, but not on the acetal resist AC1. 110 nm underexposed resolutions achieved with the resist EA4 at a mask size of 250 nm. Faster resists generally exhibit better resolution but have smaller process windows when side lobe printing is included as a criterion. Selection of a resist formulation for attenuated phase shift applications has to face a compromise between resolution, photospeed, process window and surface inhibition. Finally, ARC operational modes and optical properties had little effect on sidelobe printing, and optimization of PEB temperature is important in suppressing sidelobe printing.
The traditional lithographic approach employed by the semiconductor industry has been to pursue use of advanced prototype optical exposure tools and resists. The benefits of doing so have been: (1) The lithographic process that is used in development more closely resembles the process that will in fact be used to manufacture the chip. (2) The cost of low K1 imaging (phase-masks, off-axis illumination, and surface imaging resist) can be avoided. However with the introduction of 1Gb-dynamic random access memory (DRAM) development, a paradigm shift is being experienced within the optical lithographic community. With 1Gb-DRAMs, the minimum feature size falls irreversibly below the optical wavelength used to image the feature. Such a situation will make low K1 factor imaging unavoidable. With 175 nm groundrules typical for first generation 1G-DRAMs, K1 factors near 0.4 will be common with 0.5 as an upper limit on advanced systems currently in development irrespective of optical wavelength. This paper will cover the selection process, experimental data, and problems encountered in defining and integrating the lithographic process used to support the critical mask levels on 1Gb-DRAM development. Factors considered include: resist, masks, and illuminations via both simulation and experiment. The simulations were conducted with both internal and externally developed software. The experimental data to be reviewed was generated using an experimental 0.6 NA KrF step and scan system provided by Nikon. The resist used is commercially available from the Shipley corporation.
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