Paper
27 August 2003 Fusion-bonded mutilayered SOI for MEMS applications
David Cole, Cormac McNamara, Kumar Somasundram, Anne Boyle, Claire Devine, James McKeever, Paul McCann, Andrew Nevin
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Abstract
3-stack and 4-stack, 6" dia. multilayered SOI have been fabricated using two different processes, and the bonding ability, thickness uniformity, and stress investigated. High-quality bonding was achieved with good thickness control, independent of the fabrication method used. The stress in the overall structure was controlled by the balance between the combined stress at the oxide silicon interfaces of the SOI buried oxide layers and that exerted by the oxide on the back surface of the handle wafer. An imbalance of 0.5 μm corresponded to a generated bow of about 12 μm. The etch rate of the buried oxide was enhanced along the bonding interface, particularly in the case of an oxide-oxide join, and was found to be strongly dependent on the bond annealing temperature.
© (2003) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
David Cole, Cormac McNamara, Kumar Somasundram, Anne Boyle, Claire Devine, James McKeever, Paul McCann, and Andrew Nevin "Fusion-bonded mutilayered SOI for MEMS applications", Proc. SPIE 4876, Opto-Ireland 2002: Optics and Photonics Technologies and Applications, (27 August 2003); https://doi.org/10.1117/12.463926
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CITATIONS
Cited by 5 scholarly publications.
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KEYWORDS
Oxides

Semiconducting wafers

Interfaces

Etching

Silicon

Annealing

Scanning electron microscopy

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