Paper
21 March 1989 A Pipeline Architecture For Real-Time Connected Components Labeling
James S. J. Lee, C. Lin
Author Affiliations +
Proceedings Volume 1004, Automated Inspection and High-Speed Vision Architectures II; (1989) https://doi.org/10.1117/12.948999
Event: 1988 Cambridge Symposium on Advances in Intelligent Robotics Systems, 1988, Boston, MA, United States
Abstract
A pipeline based connected components labeling architecture is described; the algorithm (an extension of Rosenfeld et al. (1966)) and architecture were verified by software simulation. The transitive closure label equivalence process is performed by a content addressable memory. The scheme takes full advantage of the concurrent memory operations provided by content addressable memory, and performs the connected components labeling in only two pipeline frames, independent of the complexity of component shapes in the input image. The connected components labeling module can work in conjunction with the existing feature and moment extraction hardware. The pipeline based architecture allows other image processing operations to be performed in the same pipeline preceding the connected components labeling module. Thus, the connected components operations effectively take no additional operation time. This simple architecture should be low cost and easy to implement in hardware.
© (1989) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
James S. J. Lee and C. Lin "A Pipeline Architecture For Real-Time Connected Components Labeling", Proc. SPIE 1004, Automated Inspection and High-Speed Vision Architectures II, (21 March 1989); https://doi.org/10.1117/12.948999
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Cited by 1 scholarly publication.
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KEYWORDS
Content addressable memory

Image processing

Clocks

Feature extraction

Computer architecture

Computer simulations

Image segmentation

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