Design space sampling using hierarchical clustering of patterns on a full chip

Andrey Lutich

doi:10.1117/12.2257988

28 March 2017 Design space sampling using hierarchical clustering of patterns on a full chip

Andrey Lutich

Proceedings Volume 10148, Design-Process-Technology Co-optimization for Manufacturability XI; 101480T (2017) https://doi.org/10.1117/12.2257988
Event: SPIE Advanced Lithography, 2017, San Jose, California, United States

Abstract

This research considers problem of sampling design space of a given physical design layout. More specifically, it deals with extraction of a set of characteristic design patterns evenly distributed within design space occupied by the layout. The methodology reported here is capable of condensing large design layouts comprised of billions of patterns to few tens of representative cases fulfilling needs of process development and process monitoring in a semiconductor manufacturing facility as well as for OPC and process compensation setup. Patterns extracted by this method include both patterns having high representation in the incoming design and anomalous configurations. In the case study we have sampled design space of a 22FDX test chip with 40 mm² area on a contact layer. Incoming design layout comprised of 763.6 million patterns has been condensed to 61 patterns that contained all anticipated design configurations as well as a couple of unexpected findings. Extractions of compact pattern representations and multi-step hierarchical clustering method enabling full chip execution (10⁶-10¹⁰ patterns) are discussed here in detail.

Conference Presentation

Citation Download Citation

Andrey Lutich "Design space sampling using hierarchical clustering of patterns on a full chip", Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480T (28 March 2017); https://doi.org/10.1117/12.2257988

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