Track height reduction for standard-cell in below 5nm node: how low can you go?

S.M. Yasser Sherazi; Jung Kyu Chae; P. Debacker; L. Matti; P. Raghavan; V. Gerousis; D. Verkest; A. Mocuta; R.H. Kim; A. Spessot; J. Ryckaert

doi:10.1117/12.2297191

20 March 2018 Track height reduction for standard-cell in below 5nm node: how low can you go?

S.M. Yasser Sherazi, Jung Kyu Chae, P. Debacker, L. Matti, P. Raghavan, V. Gerousis, D. Verkest, A. Mocuta, R.H. Kim, A. Spessot, J. Ryckaert

Author Affiliations +

Proceedings Volume 10588, Design-Process-Technology Co-optimization for Manufacturability XII; 1058809 (2018) https://doi.org/10.1117/12.2297191
Event: SPIE Advanced Lithography, 2018, San Jose, California, United States

Abstract

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Conference Presentation

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S.M. Yasser Sherazi, Jung Kyu Chae, P. Debacker, L. Matti, P. Raghavan, V. Gerousis, D. Verkest, A. Mocuta, R.H. Kim, A. Spessot, and J. Ryckaert "Track height reduction for standard-cell in below 5nm node: how low can you go?", Proc. SPIE 10588, Design-Process-Technology Co-optimization for Manufacturability XII, 1058809 (20 March 2018); https://doi.org/10.1117/12.2297191

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