Optimization of read and write performance of SRAMs for node 5nm and beyond

Khaja Ahmad Shaik; Mohit Gupta; Pieter Weckx; Alessio Spessot

doi:10.1117/12.2515162

20 March 2019 Optimization of read and write performance of SRAMs for node 5nm and beyond

Khaja Ahmad Shaik, Mohit Gupta, Pieter Weckx, Alessio Spessot

Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096203 (2019) https://doi.org/10.1117/12.2515162
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

Scaled technology node, SRAMs suffer from increased Bit Line (BL) and Word Line (WL) resistance. To solve these issues, we present SRAM bit-level BL and WL metallization and options suitable for both SADP an EUV. We also present Buried power Rail (BPR) SRAM as enablers for high density SRAM cells (HD-111) in scaled technology nodes for 5nm and beyond and illustrate system level advantages of BPR SRAM with BPR based power delivery network of a hard macro like Arm 64-bit CPU.

Conference Presentation

Citation Download Citation

Khaja Ahmad Shaik, Mohit Gupta, Pieter Weckx, and Alessio Spessot "Optimization of read and write performance of SRAMs for node 5nm and beyond", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096203 (20 March 2019); https://doi.org/10.1117/12.2515162

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