PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.
Neuromorphic computing (NC) has emerged as one of the leading computation methodologies with low power consumption. Conventional CMOS based implementation of a complex computing system leads to power hungry, unscalable and inefficient designs. The present technologies are inefficient for computation intensive tasks such as neural networks. Hence, there is a need for unconventional devices and techniques. Nano-scale devices with the ability to mimic biological computation efficiently have been explored. Non-volatile memories such as resistive random access memory (RRAM) and phase change memory (PCM) are used for mapping synaptic functionality. Spintronic devices are among the suitable candidate to implement NC with low power consumption. Neuron as well as synapse functionality for neural networks are mapped using spin devices such as spin transfer torque magnetic random access memory (STT-MRAM) and spin orbit torque (SOT-MRAM). This paper compares the performance metrics of spin devices with other non-volatile memories for the implementation of neural network architecture with a single hidden layer. Spin device architecture consumes less area and much lower leakage power while to achieve the same level of accuracy as other devices. The MNIST dataset image classification achieved 1.17X reduction in leakage power, 9.42X reduction in latency and 1.08X reduced area consumption using SOT-MRAM device as compared to RRAM, PCM and conventional static random access memory (SRAM) respectively.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.