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Over the past few years, we have spent quite some effort to demonstrate that the off-line mask-to-mask overlay as determined on the PROVE tool correlates very well with the on-wafer overlay as measured by the scanner. The role and placement of the reticle alignment marks was considered in this analysis together with the reticle alignment model. The excellent correlation (R2 < 0.96) could only be achieved by a carefully set-up experiment. All potentially disturbing additional overlay contributors were ruled out. By doing so, a one-to-one comparison between the off-line determined mask-to-mask overlay and the on-wafer measured overlay could be made. This means that the mask-to-mask overlay as measured by PROVE directly translates into an on-product overlay contribution. The residual mismatch of ~ 0.6-nm could be attributed to the scanner itself and the sampling difference between a PROVE measurement and that of the alignment sensor inside the scanner. In this follow-up work, we will make a start to apply the knowledge that was obtained previously to a use-case that is much closer to what is common practice in the industry. An N7 equivalent technology process has been selected in combination with a state-of-the-art mask. This mask was made on an EBM-9000 system and contains μ-DBO (Diffraction Based Overlay) targets that can be readout on an ASML Yieldstar (YS:375) overlay metrology tool. Moreover, the mask contains electrical-test structures and random logic features. This makes it possible to study the onproduct overlay performance from the exposure field level down to a single logic feature on the mask! The mask is not the only contributor to the on-product overlay. Other on-product overlay contributors may be present as well. The current investigation aims to understand the on-product overlay performance by identifying the underlying contributors. This is done by considering the overlay as measured on the μ-DBO targets. The mask writing, etch, scanner, and metrology contributions are being addressed. We show that the mask contribution as part of the on-product overlay budget is comparable with the overlay performance of the state-of-the-art scanner ASML NXT:2000i (≤ 1.4-nm single machine overlay, dedicated chuck, full wafer coverage) that was used in this work. The goal of this paper is to set and understand the baseline for the intra-field on-product overlay performance as measured on YS overlay targets including all its sub-contributors. This enables us to make the next step towards local placement errors for individual device structures.
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