3.1

Requirements to Double Slit Device (SLIDS)

The geometrical requirements of Double slit device are the slit width of 84 μm and 44.1 mm in length for each slit. The tolerances are 2 μm in width and 50 μm in length, but the positions of the slits to each other and straightness of each slit are required with accuracies of less than 3 μm. The slit thicknesses must be less than 15 μm. The required slit planarity of less than 10 μm is challenging.

The interface requirements define an absolute positioning of the slits to mechanical interfaces of about 50 μm along slit length and width, but 2 arcmin along the rotational degrees of freedom (e.g. optical axis). The knowledge of slit position of 1.5 μm for linear and 10 arcsec for rotational measurements are challenging requirements for double slit device characterization.

The environmental loads were driving the design and analysis activities, because there are high shock loads (636 g at 725 Hz up to 10 kHz – tolerance -0/+6dB). The required ground to orbit stability of less than 5 μm of slits with respect to the mechanical interfaces was a challenging one during SLIDS breadboard testing.

3.2

Design of Double Slit Device

The double slit device (SLIDS) consists of a double slit upper frame and a double slit lower frame. The double slit chip will be clamped in between the upper and the lower frame. The surface of the lower frame is lapped to reach a planarity of less than 1 μm. The double slit chip will be planarized by pressing the double slit chip onto a reference plate of the lower frame using mechanical springs (double slit springs). The spring forces guarantee the planarization and the mechanical stable fixation of the double slit chip with respect to mechanical loads. The double slit springs are mounted into grooves of the double slit lower frame. The double slit chip will be additional fixed with a dot of two-component epoxy adhesive to reach the double slit position stability to thermal loads.

Figure 4:

Design of double slit device.

The material of the double slit upper and lower frame was chosen to Invar to minimize the CTE mismatch of the components – silicon at double slit chip and the frames. The Invar parts will be plated with Nickel-Phosphor as anti-corrosive plating. Additionally, those parts will be black-coated by Acktar Magic-Black for minimizing straylight effects.

3.3

Manufacturing of Double Slit Assembly

Manufacturing of slit Chip

The fabrication of the slit structure has been done by a lithographic exposure processes in combination with anisotropic selective Silicon wet-etching processes. The structure definition was performed by electron-beam lithography ensuring highest accuracy and resolution to comply with geometrical requirements.

The structuring process started from one side of a <100> Silicon wafer only. The overall lithographic process flow is shown in Figure 5. A cross section of the slit chip is shown in Figure 6:

Figure 5:

Manufacturing baseline sequence for the realization of the slits.

Figure 6:

Cross-sectional sketch of the double slit diaphragm with geometric specification

Black coating on slit chip

To achieve the reduced reflectivity, both sides of the slit substrate were coated with an Acktar Magic Black layer.

The application of the Magic Black coating was done by Acktar Advanced Coatings. The slits were covered by masks during the coating process. Investigations on Acktar Magic Black coatings inside the clear aperture of the slits were used to determine the offset the slit width including the Acktar coating tolerances. The measurements show a decrease of slit width of < 4 μm after black coating application. The slit widths were measured in 500 μm steps along the slit length of 44 mm and in 1 μm steps along 168 μm according to the specification of the slit width uniformity.

The slit width measurements were made using the Vistec LION LV1 system. The LION is a 20keV e-beam tool with a high precision laser interferometer stage for carrying up to 150 mm sized substrates and the slit-width measurements are based on pattern edge detection implemented in the software.

Figure 7:

slit width measurements before and after black coating

The averaged total hemispherical reflectance of 1.2 % was reached within a wavelength range from 400 nm to 1050 nm on polished silicon substrates of the slit chips.

Figure 8:

Total hemispherical reflectance of black coatings on slit chips

Edge radii of less than 1 μm were reached inside the slits clear apertures. Figure 9 show the surface of Acktar Magic Black coating. The required surface roughness of less than 1 μm and the sharp edge radii were reached.

Figure 9:

Image on edge radius of slit chip

Manufacturing of mechanical parts

The manufacturing of mechanical parts of the double slit device, the upper and the lower frame, was made by milling. During several manufacturing steps, the final geometries of mechanical parts were built. In between the manufacturing steps thermal treatment processes were performed to reduce the relaxation processes to meet the required manufacturing tolerances. The material Invar needs a passivation plating by Nickel-Phosphor. The interface surfaces and the surface of lower frame, which are necessary for slit chip planarization were lapped. A peak to valley planarity of less than 1 μm is required to minimize the stress induced deformation to the slit chip and to reach the slits planarity of less than 10 μm.

The maximum of the corresponding out-of-plane deformation of the slits chip amounts to 5.7μm (see Figure 10) while a maximum out of plane deformation of 3.5 μm occurs at the slit edges induced by the loads by spring forces and a surface planarity of less than 1 μm.

Figure 10:

Out-of-plane deformation of the upper and lower frame (left) and the chip (right).

Figure 11

The interface planarities of SLIDS upper (left) and lower (right) frame. The PV-Values amount to <1 micron (PV over common zone)

Assembly and Integration of Double Slit Device

The positioning of slit chip to mechanical interfaces is the most challenging task during assembly and integration of double slit device. Mounting and positioning tools were developed for mounting and positioning of upper and lower frame and slit chip. The integration and positioning concept use mechanical references of GSE for slit chip alignment. At first, the upper frame is integrated into the mounting tool. The position of upper frame will be measured and used for positioning of slit chip and lower frame. Adjustable alignment pins will define the position of slit chip and lower frame. After 1-2 iterations the slit chip will be on the required position with respect to the mechanical interfaces of lower frame. The final position will be measured by contact-less optical coordinate measurement. The required positioning accuracy of HRF slit to mechanical interfaces of less than 50 μm in x-y-coordinate and 2 arcmin in Rz was reached. If the characterization of slit chip position shows the specified values the slit chip will be fixed by a dot of two-component adhesive, applicated onto the upper frame and the slit chip.

Figure 12:

CAD image of assembly tool

Figure 13:

assembly tool with integrated upper frame and slit chip

3.4

Test of Double Slit Device

Because of the high mechanical shock loads of 636 g (-0/+6 dB) the test on double slit device breadboards were performed to prove the slit chip design and the slit chip manufacturing process chain. In an early phase a double slit device was built with a representative slit chip without black coating. The initial shock test shows no damage on the slit chip. A thermal vacuum cycling test was performed on the SLIDS-Breadboard with black coated slit chip. The shock test performed on black coated slit chip shows also no damage. For proofing the design a sine and random vibration test was performed on the uncoated double slit device.

For all tests, the built breadboards of double slit devices were used. The double slit base was manufactured representative to flight hardware. The mechanical parts of base, HR Fold mirror, LR Fold mirror and upper and lower polygons were machined as a structural dummy.

Figure 14:

SLIDS on shock test adapter

Thermal Vacuum Cycle-Test of Double Slit Device

The SLIDS is flight representative with the exception that the mechanical parts upper and lower frame are not black coated. The resulting temperature range for testing was -25°C up to +65°C.

The pressure during test was: p < 1 x 10^-5 hPa. Before the thermal vacuum test a bake out procedure was performed. The pressure during bake out was: p < 1 x 10^-5 hPa. The bake out temperature was 65 °C. The bake out was performed for 12 hours. The thermal cycles during test were performed as given below:

The SLIDS (grey part) was integrated into the thermal vacuum chamber on a thermal conductive base plate (green part) made of Aluminum) see Figure 15.

Figure 15:

SLIDS on thermal adapter – front and rear side

Up to three temperature sensors (red parts) were mounted onto the SLIDS-front and rear surfaces.

Figure 16:

SLIDS on thermal adapter of thermal vacuum chamber

Shock Test of Double Slit Device

The shock test was performed along x-, y- and z-axis. Per each axis three shocks were applied. For testing the shock setup a SLIDS – dummy without an integrated slit-chip was used. The structure of upper and lower polygon, HRF and LRF was realized by a structural dummy. The SLIDS-base and the SLITA-base was manufactured as flight representative SLITA parts. The black coatings on SLIDS-mechanical parts upper and lower frame were not foreseen. The SLIDS for shock tests were flight representative, the used screws and torques too.

Figure 17:

left: SLIDS during shock test (z-axis) – right: SPS shock levels on each axis at interface position

After shock tests the double slit device (SLIDS breadboard) were characterized and show no damage and no position deviations. Thus the manufacturing of slit chips were released on early stage. The shock test of black coated slit chip showed no damages and/or fractures.

Vibration Test of Double Slit Device

The sine vibration loads requirements are given in Table 1 and the random vibration loads requirements are given in Table 2.

Table 1:

sine vibration loads

Table 2:

random vibration loads

The vibration tests were performed along x-, y- and z-axis. Per each axis the sine and random vibration loads were applied. Acceleration sensors were mounted onto the SLIDS.

The sine vibration- and random vibration test flow were performed for x-, y- and z-axis in the following steps:

Figure 18:

sine vibration test flow

Figure 19:

random vibration test flow

Figure 20:

SILDS breadboard on shaker for vibration test – Y-axis

Test results

After thermal vacuum, shock- and sine- and random vibration tests the double slit devices were characterized. There were no damages, ruptures, cracks and/or fractures of silicon of slit chip visible during inspection using 5x and 100x magnification lens. The measurement of slits widths and lengths show no variation. No change of slit planarity (± 1 μm tolerance as success criteria) was measured. No position deviations of slit chip position with respect to mechanical interfaces of less than ± 1 μm were measured.