Design-aware virtual metrology and process recipe recommendation

Nathan G. Greeneltch; Haizhou Yin; J. Andres Torres; Melody Tao; Steven M. Lubin; Srividya Jayaram; Ivan Kissiov; Martin Niehoff; Marcus Wolf; Paul Jungmann; Todd C. Bailey

doi:10.1117/12.2661150

28 April 2023 Design-aware virtual metrology and process recipe recommendation

Nathan G. Greeneltch, Haizhou Yin, J. Andres Torres, Melody Tao, Steven M. Lubin, Srividya Jayaram, Ivan Kissiov, Martin Niehoff, Marcus Wolf, Paul Jungmann, Todd C. Bailey

Author Affiliations +

Proceedings Volume 12495, DTCO and Computational Patterning II; 124951V (2023) https://doi.org/10.1117/12.2661150
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

Modern semiconductor fabrication pushes the limits of chemistry and physics while simultaneously employing largescale, cutting-edge processing techniques. While fab expansion and capital expenditures continue to grow, the human element has become ever more demanding and prone to error. To assist with this issue, computer-aided process engineering, process control, and tool monitoring will continue to rise in the coming years. In this paper, we present an APC-integrated, customizable solution to an in-fab processing segment. Through machine learning, we combine information from design-specific extracted features with processing and metrology data to predict oxide deposition thickness. The result is a design-aware augmentation for current metrology that can recommend accurate process recipe conditions for new layouts. We also present experimental results highlighting the benefits of adding design-aware features with in-fab data to anchor and support each other across layouts and technologies. This result paves the way to decouple, isolate, and quantify the individual influences each processing step imposes on different designs at various stages of the fabrication flow.

Citation Download Citation

Nathan G. Greeneltch, Haizhou Yin, J. Andres Torres, Melody Tao, Steven M. Lubin, Srividya Jayaram, Ivan Kissiov, Martin Niehoff, Marcus Wolf, Paul Jungmann, and Todd C. Bailey "Design-aware virtual metrology and process recipe recommendation", Proc. SPIE 12495, DTCO and Computational Patterning II, 124951V (28 April 2023); https://doi.org/10.1117/12.2661150

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KEYWORDS

Data modeling

Semiconducting wafers

Metrology

Machine learning

Modeling

Fabrication

Data processing

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