Arithmetic processor design for the T9000 transputer

Simon C. Knowles

doi:10.1117/12.49824

1 December 1991 Arithmetic processor design for the T9000 transputer

Simon C. Knowles

Proceedings Volume 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II; (1991) https://doi.org/10.1117/12.49824
Event: San Diego, '91, 1991, San Diego, CA, United States

Abstract

This paper describes aspects of the arithmetic algorithms, architecture, and VLSI engineering of the 64-bit floating-point unit of the T9000 Transputer. The unit is fully conformant to the IEEE-754 floating-point arithmetic standard, and has been implemented in a 1 micrometers , triple- metal CMOS technology. The 160,000 transistor design performs addition in 40 ns, double precision multiplication in 60 ns, and double-precision division or square root in 300 ns. It will sustain 17 MFlops on the Linpac benchmark, yet occupies less than 15 mm2 of silicon--about 8.5% of the die area of T9000.

Citation Download Citation

Simon C. Knowles "Arithmetic processor design for the T9000 transputer", Proc. SPIE 1566, Advanced Signal Processing Algorithms, Architectures, and Implementations II, (1 December 1991); https://doi.org/10.1117/12.49824

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