High-voltage MOS transistors compatible with CMOS VLSI technology

Wlodzimierz Podmiotko

doi:10.1117/12.131028

1 August 1992 High-voltage MOS transistors compatible with CMOS VLSI technology

Wlodzimierz Podmiotko

Proceedings Volume 1783, International Conference of Microelectronics: Microelectronics '92; (1992) https://doi.org/10.1117/12.131028
Event: International Conference on Microelectronics, 1992, Warsaw, Poland

Abstract

In this paper high-voltage MOS transistors structures fabricated using a standard CMOS technology and a special design technique are presented. The design, characterization, and modeling of n-MOS, with the breakdown voltage of 50 V, and p-MOS, with the breakdown voltage of 130 V, fabricated using a standard 3 micrometers CMOS process are discussed. In addition, the possibility of high-voltage buffer circuit realization which is composed of n-MOS and p-MOS transistors, operating with the supply system U_SS equals 0, U_DD equals 5 V, U_E equals - 40 V, self-isolated from low-voltage components is demonstrated.

Citation Download Citation

Wlodzimierz Podmiotko "High-voltage MOS transistors compatible with CMOS VLSI technology", Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); https://doi.org/10.1117/12.131028

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available