PLD-based synthesis of digital circuits

Krzysztof Jasinski; Jerzy Kalinowski; Tadeusz Luba

doi:10.1117/12.130988

1 August 1992 PLD-based synthesis of digital circuits

Krzysztof Jasinski, Jerzy Kalinowski, Tadeusz Luba

Proceedings Volume 1783, International Conference of Microelectronics: Microelectronics '92; (1992) https://doi.org/10.1117/12.130988
Event: International Conference on Microelectronics, 1992, Warsaw, Poland

Abstract

This paper addresses development of application specific integrated circuits in field programmable technologies using programmable logic devices (PLDs). Problems in designing on PLD devices are discussed, with emphasis on device-specific constraints. As a basic shortcoming of the existing automated design tools, lack of high level design procedures optimizing the actual circuit with respect to the target PLD device architectural capabilities is indicated. To support more effective utilization of PLD device mapping, special systems that exploit argument reduction and generic logic decomposition are proposed. Problems that have been encountered in designing a PCM frame synchronization circuit are discussed, to illustrate the whole spectrum of decisions to be made by the designer.

Citation Download Citation

Krzysztof Jasinski, Jerzy Kalinowski, and Tadeusz Luba "PLD-based synthesis of digital circuits", Proc. SPIE 1783, International Conference of Microelectronics: Microelectronics '92, (1 August 1992); https://doi.org/10.1117/12.130988

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