Clock synchronization in software MPEG-2 decoder

Victor Ramamoorthy

doi:10.1117/12.263513

17 January 1997 Clock synchronization in software MPEG-2 decoder

Victor Ramamoorthy

Proceedings Volume 3021, Multimedia Hardware Architectures 1997; (1997) https://doi.org/10.1117/12.263513
Event: Electronic Imaging '97, 1997, San Jose, CA, United States

Abstract

A novel design to the problem of clock synchronization in software MPEG-2 decoders is presented. A software MPEG decoder is attractive in terms of cost and performance. However a software decoder is prone to timing uncertainty and delay jitters. By a clever use of adaptive filtering and sub sampling of time stamps, a frequency locked loop can be designed to deliver almost instantaneous capture of the unknown encoder clock frequency and with high tolerance to delay jitter. The exact analysis of the system is complex. By invoking suitable approximations, a complete design methodology is derived. Computer simulations verify the design approach illustrated.

Citation Download Citation

Victor Ramamoorthy "Clock synchronization in software MPEG-2 decoder", Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); https://doi.org/10.1117/12.263513

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