High-bandwidth and low latency from a three-dimensional reconfigurable interconnect

John W. Morris; Sonny Tham

doi:10.1117/12.359541

26 August 1999 High-bandwidth and low latency from a three-dimensional reconfigurable interconnect

John W. Morris, Sonny Tham

Proceedings Volume 3844, Reconfigurable Technology: FPGAs for Computing and Applications; (1999) https://doi.org/10.1117/12.359541
Event: Photonics East '99, 1999, Boston, MA, United States

Abstract

A high bandwidth, low latency processor interconnect has been constructed using off-the-shelf FPGAs and a small amount of additional logic. The Achilles system comprises a router in which the main circuit elements (the FPGAs) have been placed on ten small PCBs and connected together to make a router `stack' and a PCI interface. On the first prototype, channel bandwidth has been measured at 28 Mbytes/second and latency was measured to be 800 ns. The newer low-voltage FPGAs will be used in the next Achilles variant, allowing the bandwidth capability will increase to close to the theoretical maximum for PCI bus. The router stack and PCI interface also has application as a general purpose reconfigurable processor which may be arbitrarily extended by adding further stacks to the system.

Citation Download Citation

John W. Morris and Sonny Tham "High-bandwidth and low latency from a three-dimensional reconfigurable interconnect", Proc. SPIE 3844, Reconfigurable Technology: FPGAs for Computing and Applications, (26 August 1999); https://doi.org/10.1117/12.359541

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