Hybrid Cu and Al interconnects for high-performance system LSI

Hiroshi Kawashima; Motoshige Igarashi; Akihiko Harada; Hiroyuki Amishiro; Noboru Morimoto; Akihiko Ohsaki; Keiichi Higasitani; Hideaki Arima

doi:10.1117/12.360540

1 September 1999 Hybrid Cu and Al interconnects for high-performance system LSI

Hiroshi Kawashima, Motoshige Igarashi, Akihiko Harada, Hiroyuki Amishiro, Noboru Morimoto, Akihiko Ohsaki, Keiichi Higasitani, Hideaki Arima

Author Affiliations +

Proceedings Volume 3881, Microelectronic Device Technology III; (1999) https://doi.org/10.1117/12.360540
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

A high performance of 0.18 micrometers CMOS logic device has been developed with 0.15micrometers transistor and six level interconnects. Multi-level interconnect system consists of conventional process with Al wire and dual damascene process with Cu wire. It is well known that a reduction of interconnect delay time is important as the design rule is scaled. Recently low resistance Cu interconnects and low-k dielectric materials are expected to solve this problem We investigated the interconnect delay time of Cu and Al for the fine metal pitch and the coarse metal pitch, to optimize the interconnect system for 0.18 micrometers design rule generation, 4-level Al interconnects with fine metal pitch are suitable for short distance wiring such as intra-block cell to cell interconnects, whereas 2-level Cu interconnects with coarse metal pitch are used for long distance wiring such as mega-block to block interconnects to achieve high- speed and high-density system LSI devices.

Citation Download Citation

Hiroshi Kawashima, Motoshige Igarashi, Akihiko Harada, Hiroyuki Amishiro, Noboru Morimoto, Akihiko Ohsaki, Keiichi Higasitani, and Hideaki Arima "Hybrid Cu and Al interconnects for high-performance system LSI", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360540

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