Use of intentional-defect wafers for tool inspection validation

Richard J. Jarvis; Christine Chua

doi:10.1117/12.386485

2 June 2000 Use of intentional-defect wafers for tool inspection validation

Richard J. Jarvis, Christine Chua

Proceedings Volume 3998, Metrology, Inspection, and Process Control for Microlithography XIV; (2000) https://doi.org/10.1117/12.386485
Event: Microlithography 2000, 2000, Santa Clara, CA, United States

Abstract

Scan speed, defect capture, false and nuisance rate are just some of the important metrics used in evaluation inspection methodologies. With newer methodologies such as SEM-based inspection, it is difficult to find samples suitable to study these parameters as the nature of some of the defects in the sample cannot be characterized by other methods. It is for this reason that specific defects were designed and placed on a reticle set in both the array and the random logic areas of the device layout. At different layers, knowing exactly the number and placement of these 'intentional defects' allowed the assessment of scan speed, defect capture, false and nuisance rate at various process levels. This method provided a means of evaluating the inspection methodology as well as optimizing recipes to find the best capture rate at the optimum scan speeds.

Citation Download Citation

Richard J. Jarvis and Christine Chua "Use of intentional-defect wafers for tool inspection validation", Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); https://doi.org/10.1117/12.386485

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