Emerging technologies for chip-level optical interconnects

Serge Oktyabrsky; James Castracane; Alain E. Kaloyeros

doi:10.1117/12.469568

3 June 2002 Emerging technologies for chip-level optical interconnects

Serge Oktyabrsky, James Castracane, Alain E. Kaloyeros

Proceedings Volume 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging; (2002) https://doi.org/10.1117/12.469568
Event: Symposium on Integrated Optoelectronic Devices, 2002, San Jose, California, United States

Abstract

Interconnect bottleneck in emerging integrated circuitry (IC) has generated a need for alternative signal transmission solutions, such as optical technologies, in chip-level applications. The present paper discusses target parameters for chip-level optical interconnects (CLOIs) that yield superior performance starting with the 70 nm IC node, and possibly extending down to the 25-15 nm node. The benefits and disadvantages of various CLOI system and component solutions are reviewed. In particular, this paper discusses critical fundamental and technological challenges that need resolution to enable massively parallel CLOI links with a total throughput of 10-25 Tb/s, reduced power consumption in comparison with electrical wires, and enhanced density. Recent results from the presenting authors are summarized with an emphasis on CLOI specific solutions. These results include the development of InAs quantum dot gain medium to increase the operating temperature of laser arrays above that of Si ICs. Controllable routing of VCSEL- emitted beams is carried out through a microsystem-based reconfigurable free-space interconnect system which employs optical diffractive or reflective structures. This work also explores a novel hybrid integration protocol that allows self-aligned bonding of massive arrays of III-V components to Si electronics, and ensures low thermal budget and reduced stress.

Citation Download Citation

Serge Oktyabrsky, James Castracane, and Alain E. Kaloyeros "Emerging technologies for chip-level optical interconnects", Proc. SPIE 4652, Optoelectronic Interconnects, Integrated Circuits, and Packaging, (3 June 2002); https://doi.org/10.1117/12.469568

ACCESS THE FULL ARTICLE

INSTITUTIONAL
Select your institution to access the SPIE Digital Library.

SELECT YOUR INSTITUTION

PERSONAL
Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.

PERSONAL SIGN IN

No SPIE Account? Create one

PURCHASE THIS CONTENT

SUBSCRIBE TO DIGITAL LIBRARY

50 downloads per 1-year subscription

Members: $195

Non-members: $335 ADD TO CART

25 downloads per 1 - year subscription

Members: $145

Non-members: $250 ADD TO CART

PURCHASE SINGLE ARTICLE

Includes PDF, HTML & Video, when available