Lithography-driven layout of logic cells for 65-nm node

Dipankar Pramanik; Michel L. Cote

doi:10.1117/12.485349

10 July 2003 Lithography-driven layout of logic cells for 65-nm node

Dipankar Pramanik, Michel L. Cote

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.485349
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

The ITRS roadmap for the 65nm technology node, targets poly gate lengths of 65nm and poly pitches between 140-180nm. In addition, contact overlaps and spacing to diffusion contacts will need to be scaled down. It is very likely that the poly layer will be printed using 193nm high NA steppers and Strong Phase Shift Technologies. Attempts to capture the effect of RET on layout by adding more constraints to the desing rules make it difficult to lay out cells using manual tools and can also lead to sub optimal designs. In this paper we describe a methodology that couples automatic cell generation with Phase shifter insertion and image simulation to allow the design space to be explored more fully.

Citation Download Citation

Dipankar Pramanik and Michel L. Cote "Lithography-driven layout of logic cells for 65-nm node", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.485349

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