200-Mbps optical integrated circuit design and first iteration realizations in 1.2- and 0.8-micron Bi-CMOS technology

Lukas Willem Snyman; C.-T. Chaing; Alfons Bogalecki; Monuko Du Plessis; Herzl Aharoni

doi:10.1117/12.530733

1 July 2004 200-Mbps optical integrated circuit design and first iteration realizations in 1.2- and 0.8-micron Bi-CMOS technology

Lukas Willem Snyman, C.-T. Chaing, Alfons Bogalecki, Monuko Du Plessis, Herzl Aharoni

Author Affiliations +

Proceedings Volume 5357, Optoelectronic Integration on Silicon; (2004) https://doi.org/10.1117/12.530733
Event: Integrated Optoelectronic Devices 2004, 2004, San Jose, CA, United States

Abstract

A prototype Silicon CMOS Optical Integrated Circuit (Si CMOS OEIC) was designed and simulated using standard 0.8 micron Bi-CMOS silicon integrated circuit technology. The circuit consisted of an integrated silicon light emitting source, an optical wave-guiding structure, two integrated optical detectors and two high-gain CMOS transimpedance analogue amplifiers. Simulations with MicroSim PSpice software predict a utilizable bandwidth capability of up to 220 MHz for the trans-impedance amplifier for detected photo-currents at the input of the amplifier in the range of 1 nA to 100 nA and driving a 10mV to 1 V signal into a 100 kΩ load. First iteration OEIC structures were realised in 1.2 micron CMOS technology for various source-waveguide-detector arrangements. Current signal ranging from 1nA to 1 micro-amp was detected at detectors. The technology seems favorable for first-iteration implementation for digital communications on chip up to 200Mbps.

Citation Download Citation

Lukas Willem Snyman, C.-T. Chaing, Alfons Bogalecki, Monuko Du Plessis, and Herzl Aharoni "200-Mbps optical integrated circuit design and first iteration realizations in 1.2- and 0.8-micron Bi-CMOS technology", Proc. SPIE 5357, Optoelectronic Integration on Silicon, (1 July 2004); https://doi.org/10.1117/12.530733

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