A heuristic method for statistical digital circuit sizing

Stephen Boyd; Seung-Jean Kim; Dinesh Patil; Mark Horowitz

doi:10.1117/12.657499

13 March 2006 A heuristic method for statistical digital circuit sizing

Stephen Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz

Proceedings Volume 6156, Design and Process Integration for Microelectronic Manufacturing IV; 615608 (2006) https://doi.org/10.1117/12.657499
Event: SPIE 31st International Symposium on Advanced Lithography, 2006, San Jose, California, United States

Abstract

In this paper we give a brief overview of a heuristic method for approximately solving a statistical digital circuit sizing problem, by reducing it to a related deterministic sizing problem that includes extra margins in each of the gate delays to account for the variation. Since the method is based on solving a deterministic sizing problem, it readily handles large-scale problems. Numerical experiments show that the resulting designs are often substantially better than one in which the variation in delay is ignored, and often quite close to the global optimum. Moreover, the designs seem to be good despite the simplicity of the statistical model (which ignores gate distribution shape, correlations, and so on). We illustrate the method on a 32-bit Ladner-Fischer adder, with a simple resistor-capacitor (RC) delay model, and a Pelgrom model of delay variation.

Citation Download Citation

Stephen Boyd, Seung-Jean Kim, Dinesh Patil, and Mark Horowitz "A heuristic method for statistical digital circuit sizing", Proc. SPIE 6156, Design and Process Integration for Microelectronic Manufacturing IV, 615608 (13 March 2006); https://doi.org/10.1117/12.657499

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