OPC and design verification for DFM using die-to-database inspection

JungChan Kim; HyunJo Yang; JooKyoung Song; DongGgyu Yim; JinWoong Kim; Toshiaki Hasebe; Masahiro Yamamoto

doi:10.1117/12.711348

21 March 2007 OPC and design verification for DFM using die-to-database inspection

JungChan Kim, HyunJo Yang, JooKyoung Song, DongGgyu Yim, JinWoong Kim, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 6521, Design for Manufacturability through Design-Process Integration; 652117 (2007) https://doi.org/10.1117/12.711348
Event: SPIE Advanced Lithography, 2007, San Jose, California, United States

Abstract

The downscaling of the feature size and pitches of the semi-conductor device requires the improvement of device characteristics and high yield continuously. In lithography process, RET techniques such as immersion and polarization including strong PSM mask have enabled this improvement of printability and downscaling of device. It is true that optical lithography is approaching its limit. So other lithographic technique such as EUV is needed but the application is not yet available. In this point of view, the realization of lithography friendly layout enables good printability and stable process. And its scope is being enlarged and applied in most semi-conductor devices. Therefore, in order to realize precise and effective lithography friendly layout, we need full chip data feedback of design issue, OPC error and aberration and process variables. In this paper, we report the results of data feedback using new DFM verification tool. This tool enables full chip inspection through E-beam scan method with fast and accurate output. And these data can be classified with each item for correction and stability check through die to database inspection. Especially in gate process, total CD distributions in full chip can be displayed and analyzed for each target with simple method. At first we obtain accuracy data for each target and CD uniformity from hundreds of thousands of gate pattern. And second we detect a delicate OPC error by modeling accuracy and duty difference. It is difficult to get from only measurement of thousands pattern. Finally we investigated specific pattern and area for electrical characteristic analysis in full chip. These results should be considered and reflected on design stage.

Citation Download Citation

JungChan Kim, HyunJo Yang, JooKyoung Song, DongGgyu Yim, JinWoong Kim, Toshiaki Hasebe, and Masahiro Yamamoto "OPC and design verification for DFM using die-to-database inspection", Proc. SPIE 6521, Design for Manufacturability through Design-Process Integration, 652117 (21 March 2007); https://doi.org/10.1117/12.711348

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