Polar Correction: new overlay control method for higher-order intra-field error dependent on the wafer coordinates

Manabu Takakuwa; Keigo Toriumi; Nobuhiro Komine; Kazutaka Ishigo; Takuya Kono; Tetsuro Nakasugi; Tatsuhiko Higashiki

doi:10.1117/12.813490

23 March 2009 Polar Correction: new overlay control method for higher-order intra-field error dependent on the wafer coordinates

Manabu Takakuwa, Keigo Toriumi, Nobuhiro Komine, Kazutaka Ishigo, Takuya Kono, Tetsuro Nakasugi, Tatsuhiko Higashiki

Author Affiliations +

Proceedings Volume 7272, Metrology, Inspection, and Process Control for Microlithography XXIII; 72720J (2009) https://doi.org/10.1117/12.813490
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

A new overlay control method called "Polar Correction" has been developed. In the 3x nm half-pitch generation and beyond, even in the case of using a high-end optical exposure system such as immersion lithography with NA 1.3 over, the overlay accuracy becomes the most critical issue, and the accuracy below 10nm is indispensable [1]. In view of the severe overlay accuracy required, the shot-to-shot intra-field overlay control cannot be disregarded in this generation. In particular, the shot-to-shot intra-field overlay error caused by the influence of evaporation heat has been added in the immersion exposure system. However, it is impossible to correct the shot-to-shot intra-field overlay error by the conventional overlay control method. Therefore, we have developed the new overlay control method called Polar Correction for higher-order intra-field error dependent on the wafer coordinates. In this paper, we explain our new overlay control method for higher-order intra-field error, and show the simulation data and the experimental data. We believe that Polar Correction corresponds to the generation below 10nm overlay accuracy.

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Manabu Takakuwa, Keigo Toriumi, Nobuhiro Komine, Kazutaka Ishigo, Takuya Kono, Tetsuro Nakasugi, and Tatsuhiko Higashiki "Polar Correction: new overlay control method for higher-order intra-field error dependent on the wafer coordinates", Proc. SPIE 7272, Metrology, Inspection, and Process Control for Microlithography XXIII, 72720J (23 March 2009); https://doi.org/10.1117/12.813490

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KEYWORDS

Semiconducting wafers

Overlay metrology

Data corrections

Control systems

Immersion lithography

Process control

Source mask optimization

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