Practical implementation of via and wire optimization at the SoC level

Chi-Min Yuan; Guy Assad; Bob Jarvis; Marc Olivares; Lionel Riviere Cazaux; Puneet Sharma; Jayathi Subramanian; Matt Thompson; Kevin Wu

doi:10.1117/12.813396

12 March 2009 Practical implementation of via and wire optimization at the SoC level

Chi-Min Yuan, Guy Assad, Bob Jarvis, Marc Olivares, Lionel Riviere Cazaux, Puneet Sharma, Jayathi Subramanian, Matt Thompson, Kevin Wu

Author Affiliations +

Proceedings Volume 7275, Design for Manufacturability through Design-Process Integration III; 72750S (2009) https://doi.org/10.1117/12.813396
Event: SPIE Advanced Lithography, 2009, San Jose, California, United States

Abstract

In recent years, various DFM techniques are developed and adopted by the designers to improve circuit yield and reliability. The benefits from applying a DFM technique to a circuit often come at the expense of degrading other process or design attributes. In this paper, we discuss two widely deployed techniques: double vias and wire spreading/widening, show the benefits and trade-offs of their usage, and practical ways to implement them in SoC designs.

Citation Download Citation

Chi-Min Yuan, Guy Assad, Bob Jarvis, Marc Olivares, Lionel Riviere Cazaux, Puneet Sharma, Jayathi Subramanian, Matt Thompson, and Kevin Wu "Practical implementation of via and wire optimization at the SoC level", Proc. SPIE 7275, Design for Manufacturability through Design-Process Integration III, 72750S (12 March 2009); https://doi.org/10.1117/12.813396

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