Using partial reconfiguration for SoC design and implementation

Yana E. Krasteva; Jorge Portilla; Félix Tobajas Guerrero; Eduardo de la Torre

doi:10.1117/12.821718

28 May 2009 Using partial reconfiguration for SoC design and implementation

Yana E. Krasteva, Jorge Portilla, Félix Tobajas Guerrero, Eduardo de la Torre

Proceedings Volume 7363, VLSI Circuits and Systems IV; 736306 (2009) https://doi.org/10.1117/12.821718
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the paper.

Citation Download Citation

Yana E. Krasteva, Jorge Portilla, Félix Tobajas Guerrero, and Eduardo de la Torre "Using partial reconfiguration for SoC design and implementation", Proc. SPIE 7363, VLSI Circuits and Systems IV, 736306 (28 May 2009); https://doi.org/10.1117/12.821718

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