Paper
28 May 2009 A low voltage CMOS low drop-out voltage regulator
Salma Ali Bakr, Tanvir Ahmad Abbasi, Mohammas Suhaib Abbasi, Mohamed Samir Aldessouky, Mohammad Usaid Abbasi
Author Affiliations +
Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630S (2009) https://doi.org/10.1117/12.819796
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany
Abstract
A low voltage implementation of a CMOS Low Drop-Out voltage regulator (LDO) is presented. The requirement of low voltage devices is crucial for portable devices that require extensive computations in a low power environment. The LDO is implemented in 90nm generic CMOS technology. It generates a fixed 0.8V from a 2.5V supply which on discharging goes to 1V. The buffer stage used is unity gain configured unbuffered OpAmp with rail-to-rail swing input stage. The simulation result shows that the implemented circuit provides load regulation of 0.004%/mA and line regulation of -11.09mV/V. The LDO provides full load transient response with a settling time of 5.2μs. Further, the dropout voltage is 200mV and the quiescent current through the pass transistor (Iload=0) is 20μA. The total power consumption of this LDO (excluding bandgap reference) is only 80μW.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Salma Ali Bakr, Tanvir Ahmad Abbasi, Mohammas Suhaib Abbasi, Mohamed Samir Aldessouky, and Mohammad Usaid Abbasi "A low voltage CMOS low drop-out voltage regulator", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630S (28 May 2009); https://doi.org/10.1117/12.819796
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KEYWORDS
Transistors

Amplifiers

Signal to noise ratio

Resistance

Capacitors

CMOS technology

Analog electronics

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