Paper
3 April 2012 Improving lithography throughput and minimizing waste using predictive multi-area scheduling
Madhav Kidambi, Shekar Krishnaswamy, Steve Marteney, James Moyne, David Norman, Jeremy Webb
Author Affiliations +
Abstract
Many of the challenges in improving operational processes in wafer fabrication, such as throughput and on-time delivery, can be impacted by scheduling. While individual area predictive scheduling can provide significant benefit, especially for bottleneck tool sets, coordinated multiple area scheduling on top of individual area scheduling can address all of the challenges from a fab-wide optimized perspective. Thus we must leverage the technology of a predictive area scheduler into a fab-wide coordinated WIP optimization solution. In this coordinated solution the area predictive schedulers draw from the same set of scheduling services to achieve area objectives. These objectives are governed by a higher layer fab-level WIP management plan that determines how individual areas should be optimized to support overall fab scheduling objectives. In considering the implementation plan for predictive scheduling, the bottleneck process, which is oftentimes lithography, has been targeted first. As we expand the scheduling solution, we must focus on other potential bottleneck processes, and also look at processes that interact with the bottleneck process. The predictive multi-area scheduling and WIP optimization approach presented provides a framework for addressing individual area predictive scheduling as part of a coordinated effort to optimize scheduling to achieve fab-wide objectives.
© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Madhav Kidambi, Shekar Krishnaswamy, Steve Marteney, James Moyne, David Norman, and Jeremy Webb "Improving lithography throughput and minimizing waste using predictive multi-area scheduling", Proc. SPIE 8324, Metrology, Inspection, and Process Control for Microlithography XXVI, 832439 (3 April 2012); https://doi.org/10.1117/12.918699
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CITATIONS
Cited by 2 scholarly publications.
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KEYWORDS
Lithography

Semiconducting wafers

Plating

Reticles

Metrology

Manufacturing

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