Packaging challenges for integrated silicon photonic circuits

Nicola Pavarelli; Jun Su Lee; Peter A. O'Brien

doi:10.1117/12.2058559

1 May 2014 Packaging challenges for integrated silicon photonic circuits

Nicola Pavarelli, Jun Su Lee, Peter A. O'Brien

Proceedings Volume 9133, Silicon Photonics and Photonic Integrated Circuits IV; 91330F (2014) https://doi.org/10.1117/12.2058559
Event: SPIE Photonics Europe, 2014, Brussels, Belgium

Abstract

Cost-effective packaging of silicon photonic devices presents a significant bottleneck to commercialization of the technology. One way of addressing this packaging challenge is to use techniques that have been developed by the electronics industry and which also benefit from the use of advanced electronics assembly equipment. Even packaging processes such as fiber coupling can benefit from this approach, along with the hybrid integration of devices such as electronic components (e.g. modulator driver integrated circuits). In this paper, we will present developments made by our group towards achieving scalable fiber and electronic packaging processes that rely on electronic assembly techniques such as flip-chip assembly. We will also provide an overview of packaged prototypes being developed within our group for telecom and sensing applications and how these packaging technologies are now being made available to users through the ePIXfab foundry service.

Citation Download Citation

Nicola Pavarelli, Jun Su Lee, and Peter A. O'Brien "Packaging challenges for integrated silicon photonic circuits", Proc. SPIE 9133, Silicon Photonics and Photonic Integrated Circuits IV, 91330F (1 May 2014); https://doi.org/10.1117/12.2058559

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