Realizing petabit/s IO and sub-pJ/bit interconnect with silicon photonics

Keren Bergman; Vignesh Gopal

doi:10.1117/12.3013010

8 June 2024 Realizing petabit/s IO and sub-pJ/bit interconnect with silicon photonics

Keren Bergman, Vignesh Gopal

Proceedings Volume PC13030, Image Sensing Technologies: Materials, Devices, Systems, and Applications XI; PC1303005 (2024) https://doi.org/10.1117/12.3013010
Event: SPIE Defense + Commercial Sensing, 2024, National Harbor, Maryland, United States

Abstract

High-performance systems are increasingly bottlenecked by the energy and communications costs of interconnecting numerous compute and memory resources. Integrated silicon photonics offer the opportunity of embedding optical connectivity that directly delivers high off-chip communication bandwidth densities with low power consumption. Our recent work has shown how integrated silicon photonics with comb-driven dense wavelength-division multiplexing can scale to realize Pb/s chip escape bandwidths with sub-picojoule/bit energy consumption. This talk will discuss the integrated photonic link as well as the multi-chip packaging implemented to realize energy efficient high bandwidth density chip IO.

Conference Presentation

Citation Download Citation

Keren Bergman and Vignesh Gopal "Realizing petabit/s IO and sub-pJ/bit interconnect with silicon photonics", Proc. SPIE PC13030, Image Sensing Technologies: Materials, Devices, Systems, and Applications XI, PC1303005 (8 June 2024); https://doi.org/10.1117/12.3013010

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KEYWORDS

Silicon photonics

Information operations

Power consumption

Telecommunications

Computing systems

Dense wavelength division multiplexing

Integrated optics

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