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30 June 2016 Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension
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This PDF file contains the editorial “Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension” for JM3 Vol. 15 Issue 02
© 2016 Society of Photo-Optical Instrumentation Engineers (SPIE)
Alexander Starikov "Special Section Guest Editorial:Control of Integrated Circuit Patterning Variance, Part 2: Image Placement, Device Overlay, and Critical Dimension," Journal of Micro/Nanolithography, MEMS, and MOEMS 15(2), 021401 (30 June 2016). https://doi.org/10.1117/1.JMM.15.2.021401
Published: 30 June 2016
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Cited by 1 scholarly publication.
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KEYWORDS
Metrology

Overlay metrology

Control systems

Optical lithography

Process control

Integrated circuits

Lithography

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