Double self-aligned contact patterning scheme for 3D stacked logic and memory devices

B. Vincent; S. Wen; J. Ervin

doi:10.1117/12.3009858

9 April 2024 Double self-aligned contact patterning scheme for 3D stacked logic and memory devices

B. Vincent, S. Wen, J. Ervin

Proceedings Volume 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; 1295806 (2024) https://doi.org/10.1117/12.3009858
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

This paper presents a new patterning scheme that allows self-alignment of active area contacts at different z-elevations. This patterning approach can be used for various types of 3D logic and memory devices. From an incoming structure using a stack of materials with different etch selectivity, some local metal braces are first introduced at certain targeted elevations and provide a first level of contact to active device materials. The brace formations require diverse etch selectivity for the selected dielectric materials, ultra-conformal metal deposition techniques for use on buried/covered structures, and anisotropic metal etching steps. A second level of contact is then made to access those braces by using via and cavity etches followed by metal fill. This multi-level contact patterning technique is further described in this paper by first using a generic example, and then by looking at two specific applications for logic and memory, with new CFET and staircase contacting schemes, respectively.

Conference Presentation

(2024) Published by SPIE. Downloading of the abstract is permitted for personal use only.

Citation Download Citation

B. Vincent, S. Wen, and J. Ervin "Double self-aligned contact patterning scheme for 3D stacked logic and memory devices", Proc. SPIE 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, 1295806 (9 April 2024); https://doi.org/10.1117/12.3009858

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