Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)

T. Sarkar; D. Radisic; V. Vega Gonzalez; K. Stiers; C. Sheng; D. Montero; H. Jenkins; M. Demand; P. Wang; F. Lazzarino; N. Horiguchi

doi:10.1117/12.3014213

9 April 2024 Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)

T. Sarkar, D. Radisic, V. Vega Gonzalez, K. Stiers, C. Sheng, D. Montero, H. Jenkins, M. Demand, P. Wang, F. Lazzarino, N. Horiguchi

Author Affiliations +

Proceedings Volume 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII; 129580B (2024) https://doi.org/10.1117/12.3014213
Event: SPIE Advanced Lithography + Patterning, 2024, San Jose, California, United States

Abstract

In a complementary FET (CFET), n- and p-type transistors are stacked on top of each other to enable device scaling. This stacking approach requires very high aspect ratio vertical feature pattering, namely, active gate, spacer source/drain cavity and contact patterning. We report contact trench patterning and plasma etch process development for contacting bottom and top transistors relevant to middle-of-line (MOL) integration in monolithic nanosheet based CFET. First, deep trenches (M0) with aspect ratio (AR) ~13 to 15 are etched into SiO₂ dielectric layer between tall gates for routing bottom device. After the formation of bottom device, MOL contact patterning (M0T, AR ~8 to 9) for top device is performed. The main etch challenges are to preserve gate and gate spacer (SiN) and achieve good depth uniformity, especially when the M0 trench CD is reduced at tight pitches. At pitch 50nm, M0 etch development results are shown for four different etch processes (named as Etch Recipe 1 to 4) in which M0 etch depth is increased gradually targeting minimal SiN loss. To reduce gate spacer (SiN) loss, fluorocarbon plasma passivation and hydrocarbon polymer deposition step is used during M0 trench patterning.

Conference Presentation

Citation Download Citation

T. Sarkar, D. Radisic, V. Vega Gonzalez, K. Stiers, C. Sheng, D. Montero, H. Jenkins, M. Demand, P. Wang, F. Lazzarino, and N. Horiguchi "Dry etch challenges for patterning middle-of-line (MOL) contact trench in monolithic CFET (complementary FET)", Proc. SPIE 12958, Advanced Etch Technology and Process Integration for Nanopatterning XIII, 129580B (9 April 2024); https://doi.org/10.1117/12.3014213

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