A new approach to accelerate SEU sensitivity evaluation in circuits with embedded memories

M. Portela-García; M. Garcia Valderas; C. Lopez-Ongil; L. Entrena

doi:10.1117/12.822057

28 May 2009 A new approach to accelerate SEU sensitivity evaluation in circuits with embedded memories

M. Portela-García, M. Garcia Valderas, C. Lopez-Ongil, L. Entrena

Proceedings Volume 7363, VLSI Circuits and Systems IV; 73630X (2009) https://doi.org/10.1117/12.822057
Event: SPIE Europe Microtechnologies for the New Millennium, 2009, Dresden, Germany

Abstract

Current circuit complexity requires faster fault injection techniques to allow the evaluation of a high number of faults in a reasonable time. In particular, FPGA emulation has proven to be a performance effective method to analyze the behavior of digital circuits in the presence of soft errors due to SEU effects. In general, fault emulation-based solutions that use circuit instrumentation to inject faults in the literature does not consider the fault emulation in circuits with embedded memories. The few existing proposals that study this kind of circuits are oriented to inject faults in microprocessors, are slow solutions with respect to the injection in flip-flops and with a poor capacity to analyze the circuit behavior, due to the limited accessibility in memories (a word memory per clock cycle). Embedded memories are more and more usual and large in modern designs, and therefore, the emulation of the embedded memories is a problem of rising importance. The proposed models presented in this work allow the fault emulation in embedded memories, injection faults and observing their effects in a fast way.

Citation Download Citation

M. Portela-García, M. Garcia Valderas, C. Lopez-Ongil, and L. Entrena "A new approach to accelerate SEU sensitivity evaluation in circuits with embedded memories", Proc. SPIE 7363, VLSI Circuits and Systems IV, 73630X (28 May 2009); https://doi.org/10.1117/12.822057

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