NoC emulation framework based on Arteris NoC solution for multiprocessor system-on-chip

José A. Mori; Félix Tobajas; Valentín de Armas; Roberto Sarmiento

doi:10.1117/12.887474

3 May 2011 NoC emulation framework based on Arteris NoC solution for multiprocessor system-on-chip

José A. Mori, Félix Tobajas, Valentín de Armas, Roberto Sarmiento

Proceedings Volume 8067, VLSI Circuits and Systems V; 80670I (2011) https://doi.org/10.1117/12.887474
Event: SPIE Microtechnologies, 2011, Prague, Czech Republic

Abstract

The growth of complexity and the requirements of on-chip technologies create the need for new architectures which generate solutions representing a compromise between complexity and power consumption, and Quality of Service (QoS) of the communications between the cores of a System-on-Chip (SoC). Network-on-Chip (NoC) arises as a solution to implement efficient interconnections in SoC. This new technology, due to its complexity, creates the need of specialized engineers who can design the intricate circuits that NoC requires. It is possible to reduce those specialization needs by using CAD tools. In this paper, one of this tools, called Arteris NoC Solution, is used for developing the proposed framework for NoC emulation. This software includes three different tools: NoCexplorer, for high-level simulation of an abstract model of the NoC, NoCcompiler, in which the NoC is defined and generated in HDL language, and NoCverifier, which performs simulations of the HDL code. Furthermore, a validation and characterization infrastructure was developed for the created NoC, which can be completely emulated in FPGA. This environment is composed by OCP traffic generators and receptors, which also can perform measurements over the created traffic, and a store and communication module, which is responsible for storing the results obtained from the emulation of the entire system in the FPGA, and send it to a PC. Once the data is stored in the PC, statistical analyses are performed, including a comparison of mean latency from high level simulations, RTL simulations and FPGA emulations. The analysis of the results is obtained from three scenarios with different NoC topologies for the same SoC design.

Citation Download Citation

José A. Mori, Félix Tobajas, Valentín de Armas, and Roberto Sarmiento "NoC emulation framework based on Arteris NoC solution for multiprocessor system-on-chip", Proc. SPIE 8067, VLSI Circuits and Systems V, 80670I (3 May 2011); https://doi.org/10.1117/12.887474

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KEYWORDS

Network on a chip

System on a chip

Field programmable gate arrays

Clocks

Computer aided design

Telecommunications

Switches

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