Roughness has always been a key detractor of the optical losses within the silicon photonics devices. With scaling at 300mm wafer, there is an introduction of new tools such immersion lithography scanner, OPC technique that can help to drive furthermore the optical losses reduction. This study will detail the work done on characterizing multiple steps of the process (Lithography, Etch, Annealing) and using roughness tools such LER (Line Edge Roughness), LWR (Line Width Roughness) and finally PSD (Power Spectral Density) to understand the main detractor of the optical losses at each step. These data will be extracted using SEM imaging from VeritySEM 6i.
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